skrec ICRRE 2015 Session - 1; Track - 5

selective harmonic elimination for a new symmetric multilevel inverter 13/3/2015 selective harmonic elimination for a new symmetric multilevel inverter Ms. T.Preethika.,B.E.,(M.E-PED) PG Student Department of EEE Mrs. S.Menaka.,M.E.,(Ph.D) Asst. Prof Department of EEE

overview Objective Introduction Existing Topology Proposed Topology 13/3/2015 overview Objective Introduction Existing Topology Proposed Topology Harmonic Reduction Selective Harmonic Elimination Method Simulation and Results Conclusion

13/3/2015 objective To design a new topology with reduced number of switching devices. To apply Selective Harmonic Elimination for the designed topology and reduce the harmonic content of it.

Introduction Inverter are basically have 3 level. 13/3/2015 Introduction Inverter are basically have 3 level. Several inverter circuits are combined to form the MLI. Gives increased level of Output Voltage. No. of level increases pure sine wave is obtained. Applied in the areas of UPS, Induction Heating, HVDC Power Transmission and Variable frequency Drives.

Cascaded Multilevel Inverter 13/3/2015 Existing topology Cascaded Multilevel Inverter Referred MLI Topology

switching signals State No. Switching States Voltage Level 1 S1, S2 13/3/2015 switching signals State No. Switching States Voltage Level 1 S1, S2 +2Vdc 2 S1, S5 +Vdc 3 S5, S6 4 S3, S6 -Vdc 5 S3, S4 -2Vdc

13/3/2015 proposed topology The new topology is designed by eliminating one switch with its diode package. The switches are remodeled and the switching sequence is rearranged. Such that the new topology can produce high number of output level with very much reduced number of switches. The newly designed topology is applicable for only symmetric mode of operation.

13/3/2015 generalized circuit EXISTING SYSTEM PROPOSED SYSTEM

13/3/2015 switching states

parameters For N - level Number of DC Voltage Sources is given by 13/3/2015 parameters For N - level Number of DC Voltage Sources is given by Number of Switches is given by

13/3/2015 7 LEVEL topology

13/3/2015 switching pulses

voltage equation Voltage Equation for 7 level 13/3/2015 voltage equation Voltage Equation for 7 level Voltage Equation for n level

13/3/2015 harmonic reduction The harmonics are reduced using modulation techniques. The modulation is method where the signal is varied or corrected according to the additional signal parameters The modulated signals are given to the device to get proper output.

selective harmonic elimination pulse width modulation 13/3/2015 selective harmonic elimination pulse width modulation In this method, harmonics are eliminated according to the degree of the inverter which is given by where M - level of inverter. The degree of the inverter represents the number of switching angles For a desired peak output voltages, the switching angles should be obtained such that 0<δ1<δ2<δ3<π/2

13/3/2015 Contd.. Among the 'd' degrees, one is used for controlling the voltage magnitude and others for eliminating harmonics.

contd.. For 7 level SCMLI, the degree of the inverter is 3. 13/3/2015 contd.. For 7 level SCMLI, the degree of the inverter is 3. So that we can eliminate the 3rd and 5th harmonic element by solving the following equation using Newton Raphson Jacobian Matrix Method

nrjm algorithm Assuming random values for switching angles 13/3/2015 nrjm algorithm Assuming random values for switching angles Initializing mi = 0 Solving the matrix F(δ), B(mi) and J(δ) Comupute Δδ during iteration.

δ(k+1)=cos-1(abs(cos(δ(k+1)))) 13/3/2015 Contd... Switching angles are updated δ(k+1) = δ(k)+Δδ(k) Fesible switching angles are obtained δ(k+1)=cos-1(abs(cos(δ(k+1)))) Steps (3) to (6) is repeated to attain error goal Value of mi is incremented Steps (2) to (8) is repeated for the whole mi

simulation for 7 level MLI 13/3/2015 simulation for 7 level MLI Number of SDCS Sources : 3 SDCS Voltage : 100V Resistance : 100Ω Inductance : 1.25μH Output Voltage : 300V THD : 24.31%

simulink model for 7 level 13/3/2015 simulink model for 7 level

switching pulse generator 13/3/2015 switching pulse generator

13/3/2015 output & THD

13/3/2015 she modulated pulses

SHE modulated output & THD 13/3/2015 SHE modulated output & THD

13/3/2015 3 phase SMLI

13/3/2015 3 phase output & THD

Number of switch is reduced in the basic block . 13/3/2015 conclusion Number of switch is reduced in the basic block . The 5 level output is obtained using only 5 switches. No need of adding another block to increase two levels in output. Instead of adding another block with 6 switches, only one switch with its diode package and a dc source can be connected in series within the basic block.

13/3/2015 switching comparison

13/3/2015 reference [1]Ataollah Mokhberdoran and Ali Ajami, "Symmetric and Asymmetric Design and Implementation of New Cascaded multilevel Inverter Topology", IEEE Transactions on Power Electronics, DOI 10.1109/TPEL.2014.2302873. [2]A. Nami, F. Zare, A. Ghosh, and F. Blaabjerg, “A hybrid cascade converter topology with series - connected symmetrical and asymmetrical diode-clamped H-bridge cells,” IEEE Trans. Power Electron., vol. 26, no. 1, pp. 51- 64, Jan. 2011. [3]E. Babaei, “A cascade multilevel converter topology with reduced number of switches” IEEE Trans. Power Electron., vol. 23, no. 6, pp. 2657-2664, Nov. 2008. [4]Farhadi Kangarlu, Ebrahim Babaei, “A Generalized Cascaded Multilevel Inverter Using Series Connection of Sub-multilevel Inverters” IEEE Trans, Power Electron, Vol. 28, No. 2, pp.625-636, Feb 2013.

13/3/2015 contd. [5]Ebrahim Babaei, Somayeh Alilu, and Sara Laali, "A New General Topology for Cascaded Multilevel Inverters With Reduced Number of Components Based on Developed H-Bridge", IEEE Trans. Industrial Electronics, vol. 61, no. 8, pp. 3932 - 3939, Aug 2014. [6]José Rodríguez, Jih-Sheng Lai, Fang Zheng Peng "Multilevel Inverters: A Survey of Topologies, Controls, and Applications" IEEE Trans. Industrial Electronics, Vol. 49, no. 4, pp 724 - 738 AUGUST 2002. [7]Jagdish Kumar, Biswarup Das and Pramod Agarwal, “Selective Harmonic Elimination Technique for a Multilevel Inverter ”, Fifteenth National Power Systems Conference, IIT Bombay, pp. 608 - 613, Dec 2008.

13/3/2015 thank you