Final Project Report 64 points FFT

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Presentation transcript:

Final Project Report 64 points FFT Adviser: Prof. An-Wei Wu Mentor: 陳圓覺 Reporter: 洪聖揚

Outline The design of 64 points FFT RTL code The synthesis of FFT RTL code Area improving Problem encountered Future Work Conclusion

The structure of FFT RTL code Goal :reduce timing, area, and power butterfly 1.Two stages 2. BFI, BFII Combinational ckt multipliers Top module FFT 1.Parameterized twiddle factors 2.Folded twiddle factors 3. Multiplier I , Multiplier II Sequential ckt registers 1.Gate blocking 2.Non-shifted registers counter

Bits Design in FFT

The Design of Butterfly

The Design of Multiplier Parameterized twiddle factors --fixed twiddle factor bit in circuit Folded twiddle factors -- use 9 twiddle factors in Multiplier1, 3 twiddle factors in Multiplier2

Figures of Multiplier Design 9 sets of twiddle factors input Two type control signals twiddle Twiddle factor = 1+j0? Twiddle factors ‧‧‧‧‧‧‧ ‧‧‧‧‧‧‧ No Twiddle factor Yes Ｍｕｘ ‧‧‧‧‧‧‧ output ‧‧‧‧‧‧‧ multiplier

The design of Register Gate blocking skills --for reduce power non-shifted registers -- use counter to address registers

Figure of Registers Design 1 ‧‧‧ 2 ３２ Register 2 ‧‧‧ １２１６ Data to save Register 3 ‧‧‧ １２８ Register 4 １ ‧‧‧ ２４ Register 5 １ ‧‧‧ ２ Register 6 １ Control signal

Verification

Result of RTL Level Test 10 sets and calculation SQNR Lowest SQNR of test sets: 50.3dB The best three sets : 51.97, 52.92, 50.86 dB

Reducing non-useful registers The Tuning of Area Improve coding style *Tuning bits of output and internal data Reducing non-useful registers

Result After Synthesis Input bits=11 , Twiddle bits=11, Output bit=17 Area Timing Power Score 342772.218 19.73ns 12.1968 uW 133431935.3 337250.406 21.61ns 11.6524 uW 157493275.3

Problem Encountered in Design Folded data design Address registers

Problem Encountered in Synthesis Parameter & illegal design Unfamiliar with synthesis environment Gate level simulation

Future Work Tuning data for reducing area Improve Multipliers Improve clock period

Conclusion Pipeline structure is very useful in debug and design Gate blocking design is low power but much effort for best design Hardware language is not only the task of function work.