D. Breton, S. Simion February 2012 New proposal for the upgrade of the FE part of the ATLAS calorimeter trigger D. Breton, S. Simion February 2012

A few numbers about the system The front-end electronics of the LARG calorimeter has been developed and produced between 1990 and 2005. There are close to 200,000 electronics channels, running at 40MHz with a resolution of 16 bits Electronics is mounted in big crates housing up to 40 boards of 6 different types interconnected by a wide analog backplane Each board covers 49 x 41 cm² (surface > 5 VME boards !) LAL has been a major player in the game. Front-end board: general design, preamp, shaper, analog memory, gain selector, production test of half of the series (800 boards) Calibration board: design, production and tests Definition of the field control bus (SPAC) The system is currently working very well, thus permitting a precise hunting of the Higgs boson … However, with the increase in the performances of the LHC, there will soon be a limitation in the analog trigger because of the pile-up in the trigger towers => the trigger granularity has to be increased by a huge factor (~10).

Current architecture of the calorimeter FEE Detector

including the old version Current LOI proposal for the calorimeter FEE upgrade New Backplane Detector New LSBs on FEBs Current Controller Board New Tower Builder including the old version

Goals and Basics of the new proposal The goal of the upgrade (2018) is to replace the current analog calorimeter trigger system by a new digital one, improving its granularity by a factor 7 (1.1.4.1) to 10 (1.4.4.1) The old system can be kept as a backup but it’s not compatible with the increasing luminosity (soon saturating in rate with the nominal energy thresholds) As we understand it, the 2013/2014 LHC shutdown could be used to: test new ideas about the digital tower builder and start the prototyping while keeping the current trigger system working => a safe solution has to be chosen If possible cheap and not introducing stringent time constraints Basics of this new proposal: Looking for space, there is a lot available in the current Controller board In standard crates, it is ideally situated, next to the Tower Builder It could be used to house the layer sum boards (or their equivalent) and the future digitizing electronics, in addition to the current TTC + SPAC features Like for the other proposal, the LSBs on the FEB have to be changed and the backplane has to be redesigned, but the old TBB could be kept as it is Special crates are under study …

The Front-end Board (both sides are equipped) Optical Link to DAQ Gain selector ASICs 12-bit ADCs HAMAC Analog Memory Layer Sum board 3-gain Shapers Preamps Input connectors

Current Controller Board

Tower Builder Board

View of the current backplane

Possible implementation of the new proposal for the calorimeter FEE upgrade New Backplane New LSBs on FEBs New Controller/ Tower Digitizer Board New Controller/ Tower Digitizer Board Current Tower Builder Board

Advantages and constraints of the new proposal Advantages of the new proposal: We use a currently free space which relaxes the constraints on integration density We mainly focus on the design of the new solution and don’t redesign the former which anyhow won’t eventually fit the increasing luminosity requirements What has to be ready before the end of the next shutdown is reduced to: => a new backplane => the new layer sum boards on the FEBs => a new Controller Board housing an upgrade of the old layer sum boards The current Tower Builder remains unchanged => risk and cost are very limited The digital tower builder doesn’t have to be ready at the same time => it can be inserted in the crate later during a short shutdown (just replacing the new temporary controller board) Constraints: Changing for new shielded connectors on the Controller slot to get the necessary amount of 400 (284 input + 116 output) pins => doesn’t seem to be a problem with 2mm HM connectors Fitting the layer sum boards or their equivalent on the board Merging the individual clock USB connectors into a single multi-channel one

Candidate for new high density connectors ERmet™ vertical male monoblock connector dedicated to Compact-PCI systems 220 user pins (5 internal rows) Shielded (two external rows) Integrated guiding system Dimensions: 94 mm x 15.4 mm

Mixing connector types on the backplane This solution would be used for top and bottom rows Spring would have to be different here

Remarks Design of the new backplane could be started rapidly The size of the Controller board is 409,5 x 490 mm², whereas the size of the layer sum board is 90 x 28 mm². Including some margin, up to 16 LSBs fit on the vertical size of the main board If using both sides like on the current design of the FEB, all 30 necessary LSBs fit on a depth of only 90 mm When designing the first version of the new Controller Board , the schematics of the current one could be used again: It was designed with Cadence so it can be directly inserted into a new design. The only potential problem is the availability of the different circuits => to be checked. Backup solution is dismounting/resoldering if necessary. All of this has to be agreed with our colleagues from LPNHE. Predesign of the second version of the board could also start at once => the question is how to implement the prototype digitizing electronics - on the main board ? - on mezzanines ? (would permit the sharing of different tasks)

Summary We propose a new solution for the physical implemention of the Tower Digitizing electronics: It would fit in the free space on the current Controller board The latter would have to be redesigned, but this could be made in two steps: First version with the current TTC design + LSBs (or their equivalent) Second version with new TTC design + LSBs + prototype of digitizing electronics The current Tower Builder remains unchanged => risk and cost are very limited What has to be ready before the end of the 2013/2014 shutdown is reduced to: => a new backplane => new layer sum boards on the FEBs => the first version of the new Controller board as described above The second version doesn’t have to be ready at the same time => it can be inserted later during a short shutdown (just replacing the first version) We (LAL/IRFU) are ready to participate in the design of the new system (ASICs, boards) => sharing of work with other teams has to be defined