NanoCMOS Effects and Analogue Circuits University of Edinburgh Statistical Design and Verification of Analogue Systems NanoCMOS Effects and Analogue Circuits University of Edinburgh Wolfson Microelectronics

MOSFETs as analogue devices Static nano-effects Dynamic nano-effects Agenda MOSFETs as analogue devices undergraduate level! Static nano-effects Dynamic nano-effects Drift … all as “cartoon-physics”

“Normal” MOSFET Met Met Met Poly Vgs>Vt P- N+ N+ Doping is (here, exceptionally!) uniform

“Normal” MOSFET Met Met Met Poly P- N+ - N+ - - - - - <v> Terminal velocity … cf swimming through porridge <v>

“Normal” MOSFET Saturated On Off Linear Interactive MOSFET curves

Nanoscale MOSFET P- Poly Met N+

Nanoscale MOSFET P- Poly Met N+ c10-9M

Nanoscale MOSFET Crash sites Sources of statistical variability Random discrete dopants Line Edge Roughness Grains in polysilicon Combined

Device number 1 Nanoscale MOSFET Met Met Met Poly P- N+ N+ - crash sites - Device number 1

Device number 2, next door Nanoscale MOSFET Met Met Met Poly P- N+ N+ - - Device number 2, next door

Nanoscale MOSFETs - mismatch These devices are NOT THE SAME Nothing can make them the same, short of placing the dislocations, impurities and dopant atoms by hand and identically in every device The mismatch is intrinsic -

Nanoscale MOSFET Interactive MOSFET curves

Nanoscale MOSFET Current Mirror, Iin = Iout

Nanoscale MOSFET – solutions#1 - overdesign Iin Iout

Nanoscale MOSFET – solution#2? Iin Iout Iin Iout Vt  Vt nanoscale variation of Vt, K’  Systematic variation of Vt, K’ X (distance)

Trapping in MOSFETs Met Met Met Poly P- N+ N+ - - - - trap release

Many traps, micro-scale device Flicker noise Many traps, micro-scale device Constant succession of trapping and detrapping Flicker noise I t

Nanoscale MOSFET Interactive MOSFET curves

nanoscale … Random Telegraph Signal noise Few traps, nano-scale device, discontinuous Sudden discontinuities in Ids hence “Telegraph Signal “ Ids t

Nanoscale MOSFET I2 I1

no trapped charge with trapped Random doping I-V curve extraction 2 compact models (BSIM4) per device no trapped charge with trapped Random doping I-V curve extraction

Method – single trap Initialise trap states and bias conditions Two compact models: 1) trap filled 2) trap empty Select model (1) or (2) Initialise circuit SPICE simulation Store SPICE nodal voltages Recalculate trap occupancy based o probability of trapping

4-quadrant multiplier

4-quadrant multiplier

Single RTS-noisy MOSFET

30x RTS-noisy MOSFET

Negative Bias Temperature Instability (NBTI) Effects Met Met Met Poly V<0 E N- P+ P+ + + E Vdd Vgs<Vdd E→E – E Trapped charge works against Vgs E-field causing inversion is reduced Threshold Vt is raised

Negative Bias Temperature Instability (NBTI) Effects Most prevalent in pMOS devices when a negative voltage is applied to the PMOS gate this is the “stress voltage” Capture of positive charge carriers (holes) at the Si-SiO2 interface → positive (trapped) charge Threshold Voltage Vt is raised Removal of the stress removes some traps partial recovery

Negative Bias Temperature Instability (NBTI) Effects Vt of pMOSFETs at different temperatures (500MHz, Vdd = 1.2).