Chapter 3 Fabrication, Layout, and Simulation.

Slides:



Advertisements
Similar presentations
Lecture 11: MOS Transistor
Advertisements

© Digital Integrated Circuits 2nd Devices Digital Integrated Circuits A Design Perspective The Devices Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.
CSCE 612: VLSI System Design Instructor: Jason D. Bakos.
Digital Integrated Circuits A Design Perspective
Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Topics n Basic fabrication steps n Transistor structures n Basic transistor behavior.
Copyright © 2007, Pearson Education, Inc., Publishing as Pearson Addison-Wesley. Electric potential energy Electric potential Conservation of energy Chapter.
Introduction to CMOS VLSI Design Nonideal Transistors.
Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Topics n Derivation of transistor characteristics.
2. Transistors and Layout Fabrication techniques Transistors and wires Design rule for layout Basic concepts and tools for Layout.
© Digital Integrated Circuits 2nd Devices Digital Integrated Circuits A Design Perspective The Devices Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.
Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Topics n Derivation of transistor characteristics.
Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Topics n Derivation of transistor characteristics.
CSCE 613: Fundamentals of VLSI Chip Design Instructor: Jason D. Bakos.
Chapter 2 MOS Transistors. 2.2 STRUCTURE AND OPERATION OF THE MOS TRANSISTOR.
EE141 © Digital Integrated Circuits 2nd Devices 1 Digital Integrated Circuits A Design Perspective The Devices Jan M. Rabaey Anantha Chandrakasan Borivoje.
ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid MOS Transistor ECE442: Digital Electronics.
Digital Integrated Circuits© Prentice Hall 1995 Devices Jan M. Rabaey The Devices.
Topics Basic fabrication steps. Transistor structures.
Chapter 2 MOS Transistor Theory. NMOS Operation Region.
Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-1 Lectures 6, 7 and 8 Transistor Function Jan. 17, 20 and 22, 2003.
Chapter 6 Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved. High-Speed CMOS Logic Design.
MOSFET Current Voltage Characteristics Consider the cross-sectional view of an n-channel MOSFET operating in linear mode (picture below) We assume the.
EE141 © Digital Integrated Circuits 2nd Devices 1 Digital Integrated Circuits A Design Perspective The Devices Jan M. Rabaey Anantha Chandrakasan Borivoje.
CMOS VLSI Design 4th Ed. EEL 6167: VLSI Design Wujie Wen, Assistant Professor Department of ECE Lecture 3A: CMOs Transistor Theory Slides adapted from.
MOS Transistor Theory The MOS transistor is a majority carrier device having the current in the conducting channel being controlled by the voltage applied.
Analog Integrated Circuits Lecture 1: Introduction and MOS Physics ELC 601 – Fall 2013 Dr. Ahmed Nader Dr. Mohamed M. Aboudina
UNIT II : BASIC ELECTRICAL PROPERTIES
Power MOSFET Pranjal Barman.
MOS Capacitance Unit IV : GATE LEVEL DESIGN VLSI DESIGN 17/02/2009
Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.
The MOS Transistor Figures from material provided with Digital Integrated Circuits, A Design Perspective, by Jan Rabaey, Prentice Hall, 1996.
Chapter 2 MOS Transistors.
Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.
DMT 241 – Introduction to IC Layout
MOS TRANSISTOR (Remind the basics, emphasize the velocity saturation effects and parasitics) Structure of a NMOS transistor.
Prof. Haung, Jung-Tang NTUTL
Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.
Device Structure & Simulation
積體電路元件與製程 半導體物理 半導體元件 PN junction CMOS 製程 MOS 元件.
Topics Basic fabrication steps. Transistor structures.
INTRODUCTION: MD. SHAFIQUL ISLAM ROLL: REGI:
EE141 Chapter 3 VLSI Design The Devices March 28, 2003.
PowerPoint Presentations
Chapter 3 Image Slides Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Digital Integrated Circuits 10: Short-Channel MOSFETs
Digital Integrated Circuits 11: MOS Transistor Design and Modeling
Chapter 1 and 2 review CMOS Devices and models Fabrication process
Short channel effects Zewei Ding.
Chapter 1 and 2 review CMOS Devices and models Fabrication process
Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.
Last Lecture – MOS Transistor Review (Chap. #3)
Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.
Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.
Semiconductor devices and physics
Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.
EXAMPLE 7.1 BJECTIVE Determine the total bias current on an IC due to subthreshold current. Assume there are 107 n-channel transistors on a single chip,
Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.
Chapter 5 Circuit Simulation.
Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.
Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.
Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.
Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.
5/29/2019 Course Objectives This course teaches analog integrated design using CMOS Technology Analog Circuit Design.
Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.
Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.
Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.
Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.
Hangzhou Dianzi University
Dr. Hari Kishore Kakarla ECE
Chapter 4 Field-Effect Transistors
Presentation transcript:

Chapter 3 Fabrication, Layout, and Simulation

3.2 ic fabrication technology

3.2.1 Overview of IC Fabrication Process

3.2.2 IC Photolithographic Process Patterning process

3.2.2 IC Photolithographic Process Patterning process

3.2.3 Making Transistors CMOS process step 1 : step 2 : step3 :

3.2.3 Making Transistors CMOS process step 4 : step 5 :

3.2.3 Making Transistors

3.2.4 Making Wires Wire fabrication step 1 : step 2 :

3.2.4 Making Wires Wire fabrication step 3 : step 4 :

3.2.4 Making Wires

3.2.5 Wire Capacitance and Resistance

3.2.5 Wire Capacitance and Resistance

(3.1) 3.2.5 Wire Capacitance and Resistance Parallel-plate capacitance : Resistance : (3.1)

Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved. 3.2.5 Wire Capacitance and Resistance Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.

3.3 Layout basics

3.3 Layout Basics

3.3 Layout Basics

3.3 Layout Basics

3.4 Modeling the mos transistor for circuit simulation

3.4.2 Specifying MOS Transistors

3.4.2 Specifying MOS Transistors SPICE effective values : (3.2)

3.5 SPIce mos level 1 device model

(3.3) (3.4) (3.5) (3.6) 3.5 SPICE MOS LEVEL 1 Device Model Surface potential : Oxide capacitance : Body-effect parameter : Threshold voltage : (3.3) (3.4) (3.5) (3.6)

(3.7) (3.8) (3.9) 3.5 SPICE MOS LEVEL 1 Device Model Specified parameter : Current expression (linear region) (saturation) (3.7) (3.8) (3.9)

3.5 SPICE MOS LEVEL 1 Device Model Capacitance : (3.10)

(3.11) 3.5.1 Extraction of Parameters for MOS LEVEL 1 Long-channel saturation region equation : (3.11)

3.5.1 Extraction of Parameters for MOS LEVEL 1

3.6 BSIM3 model

3.6 BSIM3 Model

3.6 BSIM3 Model (2.11) (3.12) (3.13) (3.15) ( Threshold voltage (Sec. 2.3) : ) Threshold voltage : Oxide capacitance :

3.6 BSIM3 Model Parameters : Threshold voltage : (3.14) (3.16) (3.17)

3.6 BSIM3 Model

3.6 BSIM3 Model

3.6 BSIM3 Model Threshold voltage include all side-effects: Mobility : Critical field : Subthreshold current : (3.18) (3.19) (3.20) (3.21)

3.6 BSIM3 Model Capacitances : Source/Drain resistance : (3.22) (3.23)

3.7 Additional Effects in MOS Transistors

(3.24) (3.25) 3.7.2 Temperature Effects Carrier mobility : Intrinsic carrier concentration : (3.24) (3.25)

3.7.5 CMOS Latch-up

3.8 Silicon-on-insulator (SOI) technology

3.8 Silicon-on-Insulator (SOI) Technology