Description of Class Projects Spring 2017 Marek Perkowski There is similarity between any two projects. They are much based on ideas from the previous lectures in the class. All information is given to you on memory stick and on my updated webpage for class. It is expected that the teams will collaborate and exchange information, both between teams and inside the team. Each team should have a team leader that should take more responsibility to guide other people and supervise them. Believe me this is a very useful skill if you want to survive in real life. Documentation should be of high quality. Presentations should use PPT and be of high quality. Each student has to speak. In partial (H2) and final reports, each student should have his/her own section. I wrote tasks for every team, but if you want, you can add your own ideas. Even if you will not implement them, I welcome new ideas as a sign of your creativity and a proof that you understand high-level design material from the class. You are welcome to ask questions during class or/and come to me with your questions .

Project 01. Memristive Euclidean Distance Architecture Spring 2017 Marek Perkowski

What is this project about? This project is more complex than other, therefore we need 5 students in each team. There will be several teams working in parallel. Who will do the best job? The results will be highly innovative and publishable. You will design innovative architectures for supervised and unsupervised associative memories learning, using stateful IMPLY memristors. There is a literature given to you on memory stick that shows how to realize the architecture. This is also available on the webpage of this class. The project will require: Understanding VHDL (but you can use class examples plus the software from Kamela Rahman). See 003. Rahman_dissertation2016_updated file Understanding how stateful IMPLY built from memristors works. See 005. Memristive FPGA – Kamela Rahman – defense2016_v4 file and 006. Anika davidson file for explanation. The last paper teaches you how to synthesize the circuit using various methods, and explains timing. 3. Understanding the architecture on high-software level – See the paper 000. Hasegawa = final GAM temporal ESOINN paper. Also other papers by Hasegawa, 001, 002 and 004 can help, but paper 000 is the most important.

What you have to do to get an A for homework 2. Create the controller and data path, to realize and simulate other 5 architectures (in addition to what Kamela has done). This design should be done for specific CMOS FPGA. Design, using CMOS FPGA data path circuit for finding two maximum elements using concepts from the class, as explained. Simulate= exactly the same as Kamela. Synthesize= exactly the same as Kamela. Calculate power, area and delay = exactly the same as Kamela. Present a good presentation using PPT in class, each student speaks. Slides should have complete VHDL code and experimental results on simulation, power, delay and area. This would be sufficient for Homework 2.

What you have to do to get an A for final project. Complete homework 2 Understand how to design circuits, both combinational and sequential using stateful IMPLY gates. Synthesize one complete algorithm, the same way as Kamela has designed the Euclidean Distance, but with complete control and data path. You can choose any algorithm from Hasegawa’s paper. Using VHDL, create the description of logic with stateful IMPLY gates. You should assume certain delay time t0 for each pulse. The cells are pipelined and executed in parallel. Use the same method as in Kamela’s stateful memristor design. Simulate the pipeline, the results should show both pipelining and parallelism. You should calculate the delay, area and power. Make a high quality presentation at the end of class, week of finals. Each student speaks. Write a high quality report that would be used by me to write a journal paper with all of you as authors and me as the last author. Contact me with any kind of questions.

Project 02. Liskay-Huntsman Image Processor Spring 2017 Marek Perkowski

What is this project about? This project is easy if you understand pipelining, synchronization and systolic processors. We need two people. The results will be innovative and publishable. You will design an innovative architecture for a Image Processor, similar in essence to those discussed in the class. There is a literature given to you on memory stick that shows how to realize the architecture. The project will require: Understanding how to use VHDL for pipelining. Read the previous student reports. 21. Huntsman ImageProcessorReport is very good design but in System verilog. Change to VHDL and do all simulations and calculations, but not for memristors. 22. imag proc SIMD Liskay 2012 is a very good design but not synthesizable. Read the criticism by Jan Fure. You must make it synthesizable. All VHD files are attached on stick and on my webpage for class.

What you have to do to get an A for homework 2. Create the data path, to realize and simulate this architecture. This design should be done for specific CMOS FPGA. Simulate for CMOS FPGA = exactly the same as Kamela. Calculate power, area and delay for CMOS FPGA = exactly the same as Kamela. Present a good presentation using PPT in class, each student speaks. Slides should have complete VHDL code and experimental results on simulation, power, delay and area. This would be sufficient for Homework 2.

What you have to do to get an A for final project. Complete homework 2 Synthesize for CMOS FPGA = exactly the same as Kamela. The Huntsman and Liskay et al ideas must be used, but the design must be synthesizable, even if some functionality for color etc will be lost. Discuss this in class. You should calculate the delay, area and power. Demonstrate with simulation that your synthesized design works. Discuss timing. Make a high quality presentation at the end of class, week of finals. Each student speaks. Write a high quality report that would be used by me to write a journal paper with all of you as authors and me as the last author. Contact me with any kind of questions.

Spring 2017 Marek Perkowski Project 03. Kalman Filter Processor that internally uses Faddeev Algorithm Spring 2017 Marek Perkowski

What is this project about? You have to understand pipelining, synchronization and Kalman and Faddeev algorithms. We need at least three people. Four is even better. The results will be innovative and publishable. You will design an innovative architecture for a Kalman Filter processor that will use internally Faddeev algorithm There is a literature given to you on memory stick that shows how to realize the architecture. The project will require: Understanding how to use VHDL for pipelining and systolic architecture. Read the previous students report and slides. I give you 13 files with papers and slides from previous students and other authors. Especially look to report from Tejas Tapsale. His work was OK but was never completed. I want you to complete his work correctly

What you have to do to get an A for homework 2. Create the data path, to realize and simulate the systolic architecture for FADDEEV ALGORITHM ONLY. This design should be done for specific CMOS FPGA. Simulate for CMOS FPGA = exactly the same as Kamela. Synthesize for CMOS FPGA = exactly the same as Kamela. Calculate power, area and delay for CMOS FPGA = exactly the same as Kamela. Present a good presentation using PPT in class, each student speaks. Slides should have complete VHDL code and experimental results on simulation, power, delay and area. This would be sufficient for Homework 2. You have to explain to the class how the Faddeev algorithm works, you can use previous slides and papers. There is also a complete thesis of Hai Van Dinh Le from PSU Library.

What you have to do to get an A for final project. Complete homework 2 Using VHDL, create the description of complete Kalman Processor. Simulate the circuit, the results should show both pipelining and parallelism. You should calculate the delay, area and power. Demonstrate with simulation how timing works here. Make a high quality presentation at the end of class, week of finals. Each student speaks. Write a high quality report that would be used by me to write a journal paper with all of you as authors and me as the last author. Contact me with any kind of questions.

Project 04. Sumitha-Fure Image Processor Spring 2017 Marek Perkowski

What is this project about? This project can be three or even four people. You have to understand the designs of Sumitha et al and Jan Fure. Sumitha’s code is in Verilog, not VHDL . Fure’s design is in VHDL. Fure’s design of median filter was done for Liskay’s Image Processor, but now I want you to add it as component of Sumitha’s processor. It is your creative task to think how these two should be combined. Combine the two designs to one architecture. The whole combined processor can be in VHDL or in Verilog, but must be completely integrated, simulated and synthesized as one processor. I suggest VHDL because I know what was done by previous students in VHDL for this and similar projects, we need to characterize power, area and delay. Simulate. Discuss in class. The results will be innovative and publishable. There is a literature given to you on memory stick that shows how to realize the architecture. Many similar architectures are on Internet The project will require: Understanding how to use VHDL for systolic and SIMD architectures. Read the previous students report and slides. I give you files with papers and slides from previous students. Especially look to report from Sumitha. Her work was perfect and it worked. Incorporate work of Jan Fure. His work was OK but was never completed. I want you to complete his work correctly and integrate.

What you have to do to get an A for homework 2. Create the data path, to realize and simulate the architecture for Sumitha Image Processor. This design should be done for specific CMOS FPGA. Simulate for CMOS FPGA = exactly the same as Kamela. Synthesize for CMOS FPGA = exactly the same as Kamela. Calculate power, area and delay for CMOS FPGA = exactly the same as Kamela. Present a good presentation using PPT in class, each student speaks. Slides should have complete VHDL code and experimental results on simulation, power, delay and area. This would be sufficient for Homework 2. YOU have to explain to the class how Sumitha Architecture works, and what exactly was done by Ian Fure.

What you have to do to get an A for final project. Complete homework 2 Using VHDL, create the description of complete new processor that will have combined functionality of Sumitha and Fure processors. Synthesize the circuit, the results should show both pipelining and parallelism. You should calculate the delay, area and power. Demonstrate with simulation how timing works here. Make a high quality presentation at the end of class, week of finals. Each student speaks. Write a high quality report that would be used by me to write a journal paper with all of you as authors and me as the last author. Contact me with any kind of questions.