Activities in Pavia/Bergamo on Layer0 pixels Luigi Gaioni, Alessia Manazza, Massimo Manghisoni, Lodovico Ratti,Valerio Re, Gianluca Traversi, Stefano Zucca INFN Pavia, Universities of Bergamo and Pavia SuperB Workshop and kick-off meeting Elba, May 31, 2011 V. Re SuperB Workshop and kick-off meeting, Elba, May 31, 2011

R&D on SVT strips and pixels Readout chips are needed for SVT strips (layer 0-5, from short strips to long strips): we are in the process of defining the specs for these chips R&D on advanced pixel sensors for Layer0 is in progress: INMAPS (CMOS 0.18 mm) Pixels based on 3D integration V. Re SuperB Workshop and kick-off meeting, Elba, May 31, 2011

Monolithic Active Pixel Sensors in the INMAPS process (CMOS 180 nm) The deep P-well can be used to prevent parasitic charge collection by n-wells competing with the sensing electrode The technology provides epitaxial layers 5 or 12 mm thick with a maximum resistivity of 50 Ω*cm High resistivity epitaxial layers (1 kΩ*cm) 12 or 18 mm thick are also available. Deep P-well combined with high resistivity epi-layer increases the charge collection efficiency. This makes it possible to use a simple nwell diode instead of a large DNW sensor, reducing the overall noise.

INMAPS CHANNEL READOUT CHAIN Vbl=750 mV Imir=20 nA Cfb=5 fF C1=160 fF C2=25 fF All the simulations have been performed keeping CD=40 fF. In the INMAPS technology, we plan to test a fast readout architecture (“hybrid-pixel-like”, as in APSEL MAPS) with pixel-level sparsification and time stamping, which seems to fit at best the high background rate of Layer0. V. Re SuperB Workshop and kick-off meeting, Elba, May 31, 2011 4 4

V. Re SuperB Workshop and kick-off meeting, Elba, May 31, 2011 5

INMAPS prototype chip: pixel layout Ongoing studies of layout optimization for charge collection efficiency and speed On track for submission in July SuperB Workshop and kick-off meeting, Elba, May 31, 2011 V. Re

ciao 3D integrated MAPS from the first 3D-IC MPW run: still waiting for 3D chips In 2009, the Italian VIPIX collaboration submitted 3D active pixel devices in the first run of the 3DIC Consortium hosted by Fermilab. In this run, we designed 3D MAPS with two layers (“tiers”) of the 130 nm CMOS process by Chartered Semiconductor, vertically integrated with the Tezzaron interconnection technology. In January 2011, we received the first samples, before the interconnection. These 2D devices were successfully tested. V. Re SuperB Workshop and kick-off meeting, Elba, May 31, 2011 7 saluti

3D Fabrication Issues A lot of 31 wafers was fabricated Due to delays in fabrication, the 3D wafer bonding facilities were not available when the batch of wafers were ready. New wafers had 400 nm of protective nitride removed from surface and then were sent to EVG in Tempe for bonding at about 240 lb/in2 and 400 degrees C. Newly fabricated wafer with proper frame placement on the wafer R. Yarema, FEE2011, Bergamo, May 2011 SuperB Workshop and kick-off meeting, Elba, May 31, 2011 V. Re

3D Fabrication Issues After the nitride removal, three wafer pairs were bonded and all three had large unbonded areas in the center of the wafer pairs. There was not sufficient bond strength to continue with grinding one of the bonded wafers to 12 um because the wafers would break. The problem was thought to be either a small amount of nitride which was not removed or problems with the bonding machine. The unbonded wafers were sent to another EVG facility while the bonded pairs were sent to Ziptronix for analysis. One wafer pair was broken to expose the center and using a SEM a 3-7 nm thick layer was found on the wafer surface. At first the layer was thought to be nitride but an Auger electron microscope chemical analysis showed that the layer was carbon. All the unbonded wafers were then returned to Ziptronix where the carbon layer has been removed. After removing the residue the unbonded wafers were sent back to EVG in Tempe for bonding. carbon SEM image showing 3-7 nm residue on wafer surface By May 17 two new wafers pairs were bonded by EVG with better bonding results. Thinning is the next step, followed by back metal deposition R. Yarema, FEE2011, Bergamo, May 2011 SuperB Workshop and kick-off meeting, Elba, May 31, 2011 V. Re

Acoustic Microscope Image of 3D bonded Wafers Poorly bonded wafer pair Good bonded wafer pair R. Yarema, FEE2011, Bergamo, May 2011 SuperB Workshop and kick-off meeting, Elba, May 31, 2011 V. Re

VIPIX plans and designs The second 3D-IC run: VIPIX plans and designs The VIPIX collaboration is at an advanced stage in the design work for a second MPW run in the 3D Tezzaron/Chartered process. This second run will take place about 3 months after we get 3D devices from the first run, to allow enough time for testing No change in 3D integration technology is foreseen for the second run (TSV drilled at Chartered) The following devices will be included by VIPIX in the second run, targeting SuperB SVT specifications: “test beam grade” MAPS : 100x128, 50 um pitch (~32 mm2 active area) with high rate sparsified readout architecture a 3D readout chip for high resistivity pixel sensors (similar architecture) : 128x32, 50 um pitch (~10.3 mm2 active area) V. Re SuperB Workshop and kick-off meeting, Elba, May 31, 2011 11

Main front-end design features The analog section of the 3D readout chip for high resistivity pixels Main front-end design features CD [fF] (detector+bonding) 150 CF [fF] 32 C1 [fF] 25 C2 [fF] 12 Preamplifier Input Device [m/m] 18/0.25 Analog Supply [V] (AVDD) 1.5 Analog Power Dissipation [W/pixel] 10 Peaking Time [ns] (Qinject =16000 e-) 260 Charge sensitivity [mV/fC] 48 ENC [e- rms] 130 Threshold dispersion 560 (before corr.) 65 (after corr.) Block diagram of the analog front-end circuit for high resistivity pixel sensor V. Re SuperB Workshop, Frascati, April 4, 2011 12

Analog front-end for the ApselVI 3D MAPS chip (v2) CF C1 C2 VTHR VREF A(s) Design features and simulation results W/L=32/0.25, ID,PA=16 mA Total power dissipation=33 μW CD=300 fF 320 ns peaking time Charge sensitivity: 850 mV/fC ENC: 34 electrons Threshold dispersion: 103 electrons (15 e after DAC correction) V. Re SuperB Workshop, Frascati, April 4, 2011 13

The second 3D-IC run: Chip layout Getting ready for a submission about 3 month after we receive the chips from the first 3D-IC run V. Re SuperB Workshop and kick-off meeting, Elba, May 31, 2011

SuperB SVT and the AIDA project February 1st, 2011 was the kick-off date for the AIDA project, a EU-funded FP7 program addressing infrastructures for detector development for future particle physics experiments (www.cern.ch/aida). In AIDA, WorkPackage3 aims to establish a network of groups from European universities and high energy physics research institutes working collaboratively on 3D integration technology for thin pixel sensors with complex pixel-level functionality, with small pixel size and without dead regions (as needed by SVT Layer0). A major goal of AIDA WP3 is to build a demonstrator based on 3D integration. WP3 plans to follow a “via last ” approach to 3D integration to build a 2-layer device in heterogeneous technologies (e.g., high-resistivity pixel sensors and CMOS readout chips). We had a 1-day workshop in Bergamo, Italy, on May 23rd, 2011. The goal of this workshop was to begin a discussion with industries and research institutes which may provide 3D technology to the AIDA WP3 network SuperB Workshop and kick-off meeting, Elba, May 31, 2011 V. Re

AIDA WP3 and 3D companies Advanced pixel sensors based on 3D integration of 2 layers in heterogeneous technologies “via last” process, 4-side buttable device with low density interconnections in the device periphery. This kind of technology with relatively large TSVs for vertical interconnections in the external bonding pad region is available from several vendors (CEA-LETI, Fraunhofer EMFT and IZM, IMEC) SuperB Workshop and kick-off meeting, Elba, May 31, 2011 V. Re 16

An example of a 3D service we heard of in Bergamo SuperB Workshop and kick-off meeting, Elba, May 31, 2011 V. Re 17

Conclusions R&D on advanced pixels is in progress, various technologies are being explored Concerning SVT strips, real work on chip design has to start soon (two different chips are needed) V. Re SuperB Workshop and kick-off meeting, Elba, May 31, 2011 18

Backup slides V. Re

Via First Approach Through silicon Via formation is done either before or after CMOS devices (Front End of Line) processing Form vias before transistors IBM, NEC, Elpida, OKI, Tohoku, DALSA…. Tezzaron, Ziptronix Chartered, TSMC, RPI, IMEC…….. Form transistors before vias TWEPP-08

Via Last Approach Via last approach occurs after wafer fabrication and either before or after wafer bonding Zycube, IZM, Infineon, ASET… Samsung, IBM, MIT LL, RTI, RPI…. Notes: Vias take space away from all metal layers. The assembly process is streamlined if you don’t use a carrier wafer. TWEPP-08

Bonding Choices Electrical and Mechanical Bonds Fermilab experience (MIT LL) (RTI) (Tezzaron) (Ziptronix) TWEPP-08

Vertically integrated MAPS in the second 3D-IC run: APSEL Beam axis 1.6 mm 0.5 mm 0.25 mm ~ 38 Pad – pitch 130 mm Piste data line di 2 sottomatrici 0.16 mm 6.4 mm Submatrix 1: 128x50 128x100 pixel matrix 50 mm pitch Active area=32mm2 Readout=8mm2 Area~x2x area from FE32x128 5 mm 5.56 mm ~ 38 Pad – pitch 130 mm ~ 38 Pad – pitch 130 mm Submatrix 2: 128x50 Piste data line di 2 sottomatrici 0.16 mm 0.120 mm cut line 8.99 mm V. Re SuperB Workshop, Frascati, April 4, 2011 23

An example of how 3D integration is exploited in the second run: in-pixel logic with time-stamp latch for a time-ordered readout No Macropixel Timestamp (TS) is broadcast to pixels & pixel latches the current TS when is fired. Matrix readout is timestamp ordered A readout TS enters the pixel, and a HIT-OR-OUT is generated for columns with hits associated to that TS. A column is read only if HIT-OR-OUT=1 DATA-OUT (1 bit) is generated for pixels in the active column with hits associated to that TS TSComp. DATA-OUT HIT-OR-OUT This more complex in pixel logic will be implemented with 3D integration without reducing the pixel collection efficiency even improving the readout performance (readout could be data push or triggered) VHDL simulation of the data push chip (100MHz/cm2 input hit rate) Readout Effi > 99 % @ 50 MHz clock with timestamp of 200 ns. V. Re