Memory Access Instructions Load and Store Addressing Modes Memory Addressing. Base addressing mode. Load byte and store byte: lb, lbu, sb Address alignment. Big Endian, Little Endian. Load word. Store word. Load halfword. Store halfword. lw, sw, lh, lhu, sh Setting Up the base register Low order result. Portability problems Textbook P&H: Chapter 2.3,2.10, Appendix A Central Connecticut State University, MIPS Tutorial. Chapters 15,16.

Review: MIPS model 232 cells, each 8 bits MIPS memory is an array of 232 bytes. Each byte has a 32-bit address. Each byte can hold an 8-bit pattern, one of the 256 possible 8-bit patterns. The addresses of MIPS main memory range from 0x00000000 to 0xFFFFFFFF. 232 bytes Memory Size Operations Load: a bit pattern starting at a designated address in memory is copied into a register inside the processor. Store: a bit pattern is copied from a processor register to memory at a designated address. Address 32 bits General Purpose Register

Byte operations Load byte Memory byte -> Register byte Store byte 232 bytes Memory Size Load byte Memory byte -> Register byte Store byte Register byte -> Memory byte Address 32 bits Low order 3 2 1 0 General Purpose Register

Halfword operations Load halfword Store halfword Memory 2 bytes -> Register 2 bytes Store halfword Register 2 bytes -> Memory 2 bytes 232 bytes Memory Size Address 32 bits Low order 3 2 1 0 General Purpose Register

Word length operations Load word Memory 4 bytes -> Register 4 bytes Store word Register 4 bytes -> Memory 4 bytes 232 bytes Memory Size Address 32 bits Low order 3 2 1 0 General Purpose Register

Addressing Modes Addressing mode – One of several addressing regimes delimited by their varied use of operands and or addresses. The first two modes we have learned. 3. Base or displacement addressing, where the operand is at the memory location, whose address is the sum of a register and a constant in the instruction 2. Register addressing, where the operand is a register 1. Immediate addressing, where the operand is a constant within the instruction itself

Memory Instructions need Address & Register To transfer a word of data, we need to specify two things: Register: We specify this by # ($0 - $31) or symbolic name ($s0,…,$t0,…) Memory address: This is more difficult to specify. A MIPS instruction is 32 bits (always). A MIPS memory address is 32 bits (always). How can a load or store instruction specify an address that is the same size as itself ?

Offset and absolute address complicate our task Memory is a single one-dimensional array, so we can address it simply by supplying a pointer to a memory address. However very often, we want to be able to offset from this pointer. This is because sometimes we need only the relative address to refer to the memory starting from some current address. That relative address is called “offset”. +2 -3 Absolute pointer 0x00000006 Relative pointer(offset) +2 Relative pointer(offset) -3

Base address + Offset So for memory addressing we need: Either the absolute 32 bit address of the memory Or The offset (relative address) of the memory In this case to calculate the absolute address of the memory we need the offset and some current or base absolute address. +2 -3 Base Address = 0x00000006 Calculated address = 0x00000006+2=0x00000008 0x00000006-3=0x00000003

Where to keep the Base Address and Offset ? To specify a memory address specify two things: A register containing a base 32 bits address to memory A numerical offset in bytes in the instruction The desired memory address is the sum of these two values. Example: 8($t0) specifies the memory address pointed to by the value in $t0, plus 8 bytes

What looks like the memory access instruction ? Why sign extension ? offset lb rt, MemAaddress lb rt, offset (rs)

Addressing examples positive offset

Addressing examples negative offset