Wed. Aug 23 Announcements Professor Office Hours 1:30 to 2:30 Wed/Fri EE 326A You should all be signed up for piazza Most labs done individually (if not – called out in the doc) Make sure to register your clicker on blackboard We will have some questions Friday – will count for nothing, but can you can use them to verify that everything is registered. Real labs start next week Intro to tools/assembly Start looking at HW (some formatting issues will be fixed today)

Microcontroller Programming Techniques Module 1 Microcontroller Programming Techniques Tim Rogers 2017

Embedded systems in cars Learning Outcome #1 “An ability to program a microcontroller to perform various tasks” Why? IoT Embedded systems in cars

Learning Outcome #1 Architecture and Programming Model “An ability to program a microcontroller to perform various tasks” Architecture and Programming Model Instruction Set Overview Assembly Control Structures Control Structure Applications Table Lookup Parameter Passing Macros and Structured Programming How?

What makes a Microcontroller? General Purpose Embedded Whole-System Non-User-Programmable Focus on Programmability IBM Power 8 Microprocessor

Different Objectives General Purpose Embedded High-performance Need to run “anything” relatively well Less energy constrained “Limitless” Memory Silicon devoted to compute and caches Limited ability Inexpensive Limited memory Low-energy Silicon devoted to many peripherals (although core still consumes a lot)

Characteristics of general-purpose processors Interrupts mostly get in the way Virtual memory (Page Tables, TLBs) Deep cache hierarchy Large number of registers Hardware floating point Deep Pipelines/ Out of Order Exec. Complex Prediction Mechanisms Multicore Take ECE 437!

Characteristics of embedded processors Live and die by interrupts! Few registers (need to switch contexts fast) Circuitry devoted to analog Often rely on hand-tuned assembly code

Instruction Set Architectures (ISAs) Set of operations visible to the programmer ISA is the contract between the SW and HW Examples: CPU12, x86, PowerPC, ARM, SPARC, etc…

Different Types of ISAs 9S12 (ECE 362) 16-bits CISC (Complex Instruction Set Computer) RISC (Reduced Instruction Set Computer) DSPs (Digital Signal Processors)

ISA defines Interaction between processor and memory ??

Some common Architectures How to compute “Z = X + Y”: Accumulator LoadA X AddA Y StoreA Z Reg/Reg Load R1,X Load R2,Y Add R3,R1,R2 Store R3,Z 9S12 (ECE 362)

Why Freescale 68HC(s)12?? (AKA 9S12) “Relatively” Simple Introduces basic instruction set concepts Can easily analyze memory bus timing Actually used in the real world Comes from the automotive industry

Microcontroller Module You Dev Kit Boot/Run Switch Switch / LED input/output BDM connector COM port 9S12C32 D.C. power Microcontroller Module Docking Board

Overview of 9S12C32

Overview of 9S12C32 Several things to note….. The HCS12 CPU has the same architecture and programming model as the HC12

Overview of 9S12C32 Several things to note….. The 9S12C32 module has 2K of SRAM and 32K of Flash (no EEROM)

Overview of 9S12C32 Several things to note….. The 48-pin version of the chip on this module does not have Ports A & B padded out

Overview of 9S12C32 Several things to note….. External interrupt pins are on Port E

Overview of 9S12C32 Several things to note….. Real-time interrupt (RTI) module

Overview of 9S12C32 Several things to note….. Analog-to-digital (ATD) converter module – inputs are on Port PAD

Overview of 9S12C32 Several things to note….. Timer (TIM) module – I/O on Port T

Overview of 9S12C32 Several things to note….. Pulse width modulator (PWM) – here, I/O shared with TIM module on Port T MODRR register setting determines whether these Port T pins are mapped to the TIM or PWM

Overview of 9S12C32 Several things to note….. Asynchronous serial communications interface (SCI) on Port S

Overview of 9S12C32 Several things to note….. Controller area network (MSCAN) on Port M

Overview of 9S12C32 Several things to note….. Synchronous peripheral interface (SPI) on Port M

SRAM (Static Random Access Memory) Memory Uses SRAM (Static Random Access Memory) Volatile Variables Stack Buffers Test Code Flash Memory Non-Volatile App Code Static Data Vectors (reset and interrupts)

9S12C32 Memory Map Default (reset) location is 800-FFF test code, data, variables, stack 2K SRAM (mappable) Default (reset) location is 800-FFF firmware (application code) 30K Flash 8000-F7FF interrupt vectors

Overview of 68HC(S)12 Architecture

9S12 Registers Programming Model 16-bits 8-bits 8-bits Arithmetic/Logic 16-bits Pointers to memory Can add constant/register 16-bits Auto +/- 16-bits Pointer to top of stack PSH/PUL Instructions 16-bits Pointer to next instruction

Condition Code Register

ALU Condition Codes “C” – “carry/borrow” flag (carry out of the sign position for addition, complement of carry out of sign position for subtraction) “V” – “overflow” flag (set if two’s complement overflow has occurred) “Z” – “zero” flag (set if result of computation is zero) “N” – “negative” flag (most significant bit (sign) of computation) “H” – “half carry” flag (carry out of the lower 4-bits (nibble), only valid after ADD)

Machine Control Condition Codes “ I ” – “IRQ interrupt mask” “0” – IRQ is not masked (enabled) “1” – IRQ is masked (disabled) “X” – “XIRQ interrupt mask” “0” – XIRQ is not masked (enabled) “1” – XIRQ is masked (disabled) “S” – “STOP instruction disable” “0” – STOP instruction is enabled “1” – STOP instruction is disabled

Instruction Representation Just a bunch of bits Remember? Simple Computer?

Instruction Formats and Data Types Example Opcode (1B) Post-byte Offset (2B) – can also be 1B Immediate (2B) – can also be 1B BRSET oprx16,xysp, msk8, rel8 Opcode (1B) Post-byte ADDA addr *There are different ways to mix/match these opcode (2B) DAA Opcode (1B) DEX Length: 1B to 6B

Instruction Formats and Data Types Bit Byte (8-bit) Word (16-bit) Double Word (32-bit) Packed Binary Coded Decimal Unsigned Fractions

?? Addressing Modes Memory Addr Value 1 Value not possible 2 ADDA addr 255 Purpose: Need to access memory Need an ADDRESS 1 ?? Value not possible 270 2 ADDA addr 69 65535

Addressing Modes Definition: The CPU uses an addressing mode to determine the effective address of where an operand is stored in memory Commonly used addressing modes “immediate” (data immediately follows opcode, i.e., is part of the instruction) DOES NOT GO TO MEMORY “extended / absolute” (absolute address of where operand is stored in memory) “relative” (desired location is calculated relative to the current value in the PC) “indexed” (an index register is used to point to the operand – many variations with offset) “indirect” (the operand pointer is in memory)

Illustrative Instructions LDAA addr “load accumulator A with the contents of memory location addr” STAA addr “store the contents of accumulator A at memory location addr” addr represents the effective address

LD versus Store Memory Addr Value 1 65535 LDAA 1 A STAB 65535 B Core 255 Registers LDAA 1 77 1 A 56 56 B STAB 65535 65535 69