SAR ADC Tao Chen

Successive-approximation Register (SAR) ADC Chapter 17 Figure 05 Read chapter 17.2

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Example timing diagram At “convert start”, SHA grabs a sample and hold its value Set DAC MSB to 1 as test bit, rest bits set to 0, DAC output compared to sample held If comparator output = 1, keep test bit as 1, else set test bit = 0 If test bit is LSB, reset “busy” and signal end of conversion Else, move test bit to next lower bit, and set it to 1, generate DAC output At end of conversion, DAC input code sent out as ADC output code

Charge redistribution implementation

Sampling Phase Vin = 1.3 Vref = 5V

Conversion Phase 0 Vin = 1.3V Vref = 5V

Conversion Phase 1 Vin = 1.3 Vref = 5V

Conversion Phase 2 Vin = 1.3 Vref = 5V 1

Conversion Phase 3 Vin = 1.3 Vref = 5V

For N-bit ADC Conversion Phase 0 can be skipped Non-overlapping Clock

Chapter 17 Figure 10

Segmented CDAC

Hybrid ADC

Hybrid ADC

Design Consideration Comparator: high speed, high resolution Capacitor: matching & KT/C (area) Switch: sampling time & conversion time

Project State-of-the-art ADCs R-string R2R Flash SAR Size R CDAC (size C) Segmentation Decoder Comparator Switch Encoder SAR Logic Buffer Bubble rm Clock/Timing Power ENOB Speed Area State-of-the-art ADCs http://web.stanford.edu/~murmann/adcsurvey.html

Simulation Data converter simulation is very slow! Histogram test, spectral test takes hours to days! Server load is high at the end of the semester! Server crashes very often !! Start your project earlier !!!