Journées VLSI-FPGA-PCB Juin 2010 Xiaochao Fang IMOTEP-AD: a 64-Channel Front-End for Small Animal Positron Emission Tomography Imaging Journées VLSI-FPGA-PCB Juin 2010 Xiaochao Fang

Conclusions & perspectives Outline Introduction Circuit overview Analog part design Digital part design Test results Conclusions & perspectives xiaochao.fang@ires.in2p3.fr Journées VLSI-PCB-FPGA de l'IN2P3-Juin 2010

Efficacité de détection INTRODUCTION μCT μSPECT μPET 60cm 15 % PLATEFORME D’IMAGERIE IN VIVO DU PETIT ANIMAL AMISSA Efficacité de détection Résolution spatiale 1 mm3 xiaochao.fang@ires.in2p3.fr Journées VLSI-PCB-FPGA de l'IN2P3-Juin 2010

INTRODUCTION Total channels: Solution: 768 * 8 = 6144 24 * PCB cards * 4 * 64-channel chips Face photocathode Face anodes matrix 32*24 of crystals LYSO PLANACON 32*32 xiaochao.fang@ires.in2p3.fr Journées VLSI-PCB-FPGA de l'IN2P3-Juin 2010

Specification of IMOTEPAD Energy and time stamp measurement in one circuit 64 channels Operating range: few fC to upper than 100 pC Temporal resolution < 1ns Frequency of reading: 100 kHz Technology: CMOS AMS 0.35 µm xiaochao.fang@ires.in2p3.fr Journées VLSI-PCB-FPGA de l'IN2P3-Juin 2010

Circuit overview Analog part: IMOTEPA Digital part: IMOTEPD JTAG & DAC Energy measurement Prototype of 10 channels64 channels Digital part: IMOTEPD Digitization of time stamp Prototype of 16 channels64 channels JTAG & DAC Chip configurations & bias LVDS Receive the reference clock & readout clock Send digital data with the frequency of 125 MHz xiaochao.fang@ires.in2p3.fr Journées VLSI-PCB-FPGA de l'IN2P3-Juin 2010

Energy measurement Preamplifier Integrator: tint = 1 µs Low input impedance: 180 Ω Decrease the crosstalk Wide bandwidth: 500 MHz Current comparator less sensitive with parasite capacitance Integrator: tint = 1 µs Maximization of charges integrated Increase the energy resolution Avoid pile-up problem Sample and hold: 2 analog memories Delete completely the dead time xiaochao.fang@ires.in2p3.fr Journées VLSI-PCB-FPGA de l'IN2P3-Juin 2010

Time-to-Digital Converter Specification: time resolution<1 ns Coarse time (9 bits) Counters of 9 bits Clock of 50 MHz  step: 20 ns 2 counters  avoid metastable status Fine time (5 bits) Delay-Locked Loop (DLL) with 32 delay cells Bin size: 625 ps Encoder: 32 bits5 bits Coarse Time Fine Time Erreur Hold LSB MSB xiaochao.fang@ires.in2p3.fr Journées VLSI-PCB-FPGA de l'IN2P3-Juin 2010

Delay-Locked Loop DLL Minimize the jitter VCDL, Phase Detector, Charge Pump, Loop filter Minimize the jitter Icp = 10 µV; Cfiltre = 90 pF Fail-to-lock or false-lock problems Initialization controller xiaochao.fang@ires.in2p3.fr Journées VLSI-PCB-FPGA de l'IN2P3-Juin 2010

Test results (IMOTEPA) Dynamic range few fC ~ >100 pC Shaping time 280 ns Integral Non Linearity INL<3% Noise RMS 300 µV Input impedance 180 Ω Output transient responses of the shaper INL of channels according to injected charges xiaochao.fang@ires.in2p3.fr Journées VLSI-PCB-FPGA de l'IN2P3-Juin 2010

Test results (IMOTEPAD) Difference energy at output when using different analog memory Asymmetry of capacitances in layout Energy from capacitance 1 Energy from capacitance 2 xiaochao.fang@ires.in2p3.fr Journées VLSI-PCB-FPGA de l'IN2P3-Juin 2010

Test results (IMOTEPAD) The performances are degraded when the number of channel increase Problem of power line distribution ? The last channels (not work at all) The channels close to the first one (work well) The channels close to the last ones (not work for a large bias current) connected Energy measured according to the bias current of the amplifier xiaochao.fang@ires.in2p3.fr Journées VLSI-PCB-FPGA de l'IN2P3-Juin 2010

Test results (IMOTEPD) Code density test from the collection of the 640,000 events Clkref of 50 MHzbin size of 625 ps INL < ±0.31 LSB; DNL < ±0.17 LSB RMS Jitter < 42 ps Clk sampled by hit to select Coarse time: Synchronization between fine and coarse time Jitter of coarse time Errors on increment of the coarse time xiaochao.fang@ires.in2p3.fr Journées VLSI-PCB-FPGA de l'IN2P3-Juin 2010

Test results (IMOTEPAD) Normal case Delay of fine time ≈ 2.5 ns Delay of counters ≈ 4.5 ns Error of Coarse time every half period Buffering problem of counters delay>12 ns xiaochao.fang@ires.in2p3.fr Journées VLSI-PCB-FPGA de l'IN2P3-Juin 2010

Conclusions & perspectives Characteristics IMOTEPA (10 channels) IMOTEPD (16 channels) IMOTEPAD (64 channels) IMOTEPAD_V2 Analog Dynamic range few fC to 104 pC ─ √ Crosstalk < 0.2% Input impedance 180 Ω Power consumption 15 mW/channel 2.5 mW/channel 16.8 mW/channel CR-RC peaking time 280 ns Non-linearity < 3% RMS Noise 300 µV Gain 13.1 mV/pC Uniformity of analog memory Uniformity of channels TDC Jitter (rms) 42 ps 120 ps DNL (LSB) ± 0.17 ± 0.2 INL (LSB) ± 0.31 ± 0.5 Coarse time selection xiaochao.fang@ires.in2p3.fr Journées VLSI-PCB-FPGA de l'IN2P3-Juin 2010

Thank you for your attention xiaochao.fang@ires.in2p3.fr Journées VLSI-PCB-FPGA de l'IN2P3-Juin 2010