Clock & Data Recovery Performance testing use MATLAB

Outline CDR Architecture & simulation flow Noise Jitter Model CDR Jitter tolerance & Performance limited Furture Work

CDR Architetcure Mapping RTL-Verilog to Matlab code. Verify with “Verilog model test pattern” .

Simulation Flow Simulation Flow

Noise Jitter Model USB2.0 specification:EYE pattern “Universal Serial Bus Specification” page.131

Noise Jitter Model USB2.0 specification:EYE pattern “Universal Serial Bus Specification” page.134

Noise Jitter Model Jitter Model

Noise Jitter Model Sinusoildal Jitter modulation [1] J. Kim, D-K. Jeong, “Multi-Gigabit-Rate Clock and Data Recovery Based on Blind Oversampling,” IEEE Communications Mag., Dec. 2003, pp.68-74 [2] Jitter generation and measurement with off-the-shelf test equipment . Slobodan Milijevic, Zarlink Semiconductor [3] B. J. Lee, M.S. Hwang, J. Kim, DK. Jeong“A Quad 3.125Gbps Transceiver Cell with All-Digital Data Recovery Circuits,”IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp.384-387, 2005

Noise Jitter Model Jitter add

Noise Jitter Model Sinusoildal Jitter modulation Matlab simulation with sin Jitter Offset=0.15UI , Jitter Frequency=60MHz Unjittered Data Jittered Data Sin Jitter source

Noise Jitter Model EYE pattern with Jitter-add Matlab simulation EYE pattern with Jitter Offset=0.15UI , Jitter Frequency=6MHz Unjittered Data Jittered Data USB20 spec. EYE pattern(0.15UI)

CDR Jitter tolerance Simulation Result Jitter Offset=0.27UI , Jitter Frequency=24MHz

CDR Jitter tolerance Weight Modification

CDR Jitter tolerance Simulation Result W: Windows Size

Furture Work Make Jitter Model more accurate. Tune CDR Low Frquency & High Frequecny jitter-tolerance Performance & Area cost trade-off.