Figure 1.1. A silicon wafer..

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Presentation transcript:

Figure 1.1. A silicon wafer.

Figure 1.2. A field-programmable gate array chip. Group of 8 logic cells Memory block Interconnection wires Figure 1.2. A field-programmable gate array chip.

Please see “portrait orientation” PowerPoint file for Chapter 1 Figure 1.3. The development process.

Figure 1.4. The basic design loop. Design concept Initial design Simulation Redesign No Design correct? Yes Successful design Figure 1.4. The basic design loop.

Figure 1.5. A printed circuit board.

Please see “portrait orientation” PowerPoint file for Chapter 1 Figure 1.6. Design flow for logic circuits.

Figure 1.7. Completion of PCB development. Implementation Build prototype Testing Modify prototype Yes No Correct? Minor errors? Yes No Finished PCB Go to A, B, C, or D in Figure 1.6 Figure 1.7. Completion of PCB development.