Search-Based Synthesis of Approximate Circuits Implemented into FPGAs

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Presentation transcript:

Search-Based Synthesis of Approximate Circuits Implemented into FPGAs Zdeněk VAŠÍČEK, Lukáš SEKANINA Brno University of Technology, Faculty of Information Technology Božetěchova 1/2, 612 66 Brno - Královo Pole vasicek@fit.vutbr.cz

Introduction Approximate computing paradigm Our goal The requirement of exact numerical or Boolean equivalence between the specification and implementation of a circuit is relaxed in order to achieve improvements in performance or energy efficiency [Venkatesan et al., 2011]. The requirement of exactness can be relaxed because of: limited perceptual capability of humans a golden result is impossible (or difficult) to define Our goal To introduce a new systematic approach for the approximation and optimization of circuits intended for LUT-based FPGAs.

Principle of the proposed approach In order to deliver a good trade-off between the quality of processing and implementation cost, our method employs a genetic programming-based optimization engine. The optimization engine applies various transformation rules on a given circuit and gradually modifies the circuit with aim to obtain its approximate version which satisfies a given condition (e.g. maximal error). candidate circuit 1 HD 81.25% | EP 13/16 candidate circuit 4 HD 18.75% | EP 3/16 2 GATES candidate circuit 3 HD 18.75% | EP 3/16 HD 0% | EP 0 candidate circuit 2 original (accurate) circuit 5 GATES RESULT: error 18.8% reduction: 60% GOAL: approx. ~ 20% error

Results The proposed method was evaluated on more than 40 circuits (24 included in the paper) taken from LGSynth, ITC and ISCAS benchmark sets. Performance of five FPGA design tools was evaluated (four commonly available commercial and one state-of-the-art academia tool) The current state-of-the-art synthesis tools provide (for some instances) the results that are far from an optimum (in average,16.3% reduction was achieved). For example, a 40% reduction (68 LUTs) was achieved for ‘clmb‘ benchmark circuit (Bus Interface) without introducing any error. In average, 35.8% reduction can be obtained by introducing only a 0.2% error.

Thank you for your attention!