High-Level Hardware-Software Co-design of an 802

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Presentation transcript:

High-Level Hardware-Software Co-design of an 802 High-Level Hardware-Software Co-design of an 802.11a Transceiver System using Zynq SoC Benjamin Drozdenko Graduate Research Assistant & Ph.D. Candidate Advisors: Prof. Leeser (RCL) & Prof. Chowdhury (GENESYS) Northeastern University, Boston, MA New England Workshop on Software Defined Radio (NEWSDR) June 3, 2016 Begin with “Good afternoon, and thank you for having me here today. My name is…” Mention both advisors and labs, and what they stand for. Mention who’s funding you—MathWorks. Acknowledgments:

Wireless Transceivers: Prevalence and Challenges Surge in wireless devices 10B devices today, 50B by 2050 $14 trillion business over next 10 years 2.4, 5.8 GHz: 802.11a/b Designated ISM Bands LTE Wi-Fi 54-60, 76-88, 470-698 MHz: 802.11af TV Whitespace Reuse Challenges: Times Change C1: Adapt to changing protocols to handle contention C2: Maintain/increase bit rates C3: Decrease energy usage and error rates 3.55-3.65 GHz: Military RADAR Reuse C4: Change center frequency to use new bandwidths

HW-SW Prototyping Platform: Software Tools HDL Coder: Create HW Description Language (HDL) code Vivado: Synthesize, Implement, and Generate FPGA Bitstream Embedded Coder: Generate C code for ARM Processor MathWorks Simulink™ Model FPGA Zynq SoC CPU Transmit Path Embedded Coder™ 1 2 3 4 5 6 Ethernet (to CPU) C Code ARM Executable Receive Path 7 6 5 4 3 2 HDL Coder™ JTAG (to FPGA) HDL Code FPGA Bitstream Xilinx Vivado® Host PC: Runs SW Tools Zynq-Based Heterogeneous Computing System

Modeling the HW-SW Divide Point: 7 Model Variants SW HW V6 SW HW V5 SW HW V4 SW HW V3 SW HW V2 SW HW V1 SW HW Tx Path 1: Additive Scrambling 2: Convolutional Encoding 3: Block Interleaving 4: Digital (BPSK) Modulation 5: OFDM Modulation 6: Preamble Insertion Rx Path 1: Preamble Detection 2: OFDM Demodulation 3: Digital Demodulation 4: Block Deinterleaving 5: Viterbi Decoding 6: Descrambling FPGA Zynq SoC CPU Transmit Path 1 2 3 4 5 6 Receive Path 6 5 4 3 2 1 Zynq-Based Heterogeneous Computing System V1: SW-only model V4: Adds Tx4 & Rx3 to HW V2: Adds Tx6 & Rx1 to HW V5: Adds Tx3 & Rx4 to HW V3: Adds Tx5 & Rx2 to HW V6: Adds Tx2 & Rx5 to HW V7: HW-only model