Tutorial Nine Cache CompSci 210 - Semester One 2016.

Slides:

Advertisements

Similar presentations

Cache Memory Exercises. Questions I Given: –memory is little-endian and byte addressable; memory size; –number of cache blocks, size of cache block –An.

Advertisements

Practical Caches COMP25212 cache 3. Learning Objectives To understand: –Additional Control Bits in Cache Lines –Cache Line Size Tradeoffs –Separate I&D.

Using one level of Cache:

Homework 2 Review Cornell CS Calling Conventions int gcd(int x, int y) { int t, a = x, b = y; while(b != 0) { t = b; b = mod(a, b); a = t; } return.

The Lord of the Cache Project 3. Caches Three common cache designs: Direct-Mapped store in exactly one cache line Fully Associative store in any cache.

CS61C L31 Caches II (1) Garcia, Fall 2006 © UCB GPUs >> CPUs?  Many are using graphics processing units on graphics cards for high-performance computing.

6/12/2015Page 1 Exploiting Memory Hierarchy Chapter 7 B.Ramamurthy.

How caches take advantage of Temporal locality

Memory Hierarchies Exercises [ ] Describe the general characteristics of a program that would exhibit very little spatial or temporal locality with.

COMP3221: Microprocessors and Embedded Systems Lecture 26: Cache - II Lecturer: Hui Wu Session 2, 2005 Modified from.

Configuration Information Discuss caches with properties … 32-bit addresses 16-byte lines 256-byte capacity Memory references are either Read/Write.

Computer ArchitectureFall 2007 © November 12th, 2007 Majd F. Sakr CS-447– Computer Architecture.

Caches The principle that states that if data is used, its neighbor will likely be used soon.

COMP3221 lec34-Cache-II.1 Saeid Nooshabadi COMP 3221 Microprocessors and Embedded Systems Lectures 34: Cache Memory - II

Direct Map Cache Tracing Exercise. Exercise #1: Setup Information CS2100 Cache I 2 Memory 4GB Memory Address 310N-1N Block Number Offset 1 Block = 8 bytes.

CDA 3103 Computer Organization Review Instructor: Hao Zheng Dept. Comp. Sci & Eng. USF.

CSCE 212 Quiz 11 – 4/13/11 Given a direct-mapped cache with 8 one-word blocks and the following 32-bit memory address references: 1 2, ,

COEN 180 Main Memory Cache Architectures. Basics Speed difference between cache and memory is small. Therefore:  Cache algorithms need to be implemented.

Caches – basic idea Small, fast memory Stores frequently-accessed blocks of memory. When it fills up, discard some blocks and replace them with others.

Caches – basic idea Small, fast memory Stores frequently-accessed blocks of memory. When it fills up, discard some blocks and replace them with others.

Paging Examples Assume a page size of 1K and a 15-bit logical address space. How many pages are in the system?

Ch. 12 Cache Direct Mapped Cache. Comp Sci mem hierarchy 2 Memory Hierarchy Registers: very few, very fast cache memory: small, fast main memory:

1 CMPE 421 Advanced Computer Architecture Accessing a Cache PART1.

CPE432 Chapter 5A.1Dr. W. Abu-Sufah, UJ Chapter 5A: Exploiting the Memory Hierarchy, Part 2 Adapted from Slides by Prof. Mary Jane Irwin, Penn State University.

ACOE2011 Cache memory Homework – Q1 A computer has a 32 bit address and a 64 bit data bus with address resolution to the byte level. The computer is using.

Computer Science and Engineering Copyright by Hesham El-Rewini Advanced Computer Architecture CSE 8383 January Session 2.

B. Ramamurthy.  12 stage pipeline  At peak speed, the processor can request both an instruction and a data word on every clock.  We cannot afford pipeline.

Chapter 91 Logical Address in Paging  Page size always chosen as a power of 2.  Example: if 16 bit addresses are used and page size = 1K, we need 10.

Lecture Objectives: 1)Explain the relationship between miss rate and block size in a cache. 2)Construct a flowchart explaining how a cache miss is handled.

1 Chapter Seven. 2 Users want large and fast memories! SRAM access times are ns at cost of $100 to $250 per Mbyte. DRAM access times are ns.

11 Intro to cache memory Kosarev Nikolay MIPT Nov, 2009.

1 Chapter Seven. 2 Users want large and fast memories! SRAM access times are ns at cost of $100 to $250 per Mbyte. DRAM access times are ns.

Additional Slides By Professor Mary Jane Irwin Pennsylvania State University Group 1.

Cache Operation.

Cache Small amount of fast memory Sits between normal main memory and CPU May be located on CPU chip or module.

CSE 351 Caches. Section Feedback Before we begin, we’d like to get some feedback about section If you could answer the following questions on the provided.

1 Bits, Bytes, Binary & Hex CIS TAG ▪ Byte Bit.

Memory Hierarchy and Cache Design (3). Reducing Cache Miss Penalty 1. Giving priority to read misses over writes 2. Sub-block placement for reduced miss.

نظام المحاضرات الالكترونينظام المحاضرات الالكتروني Cache Memory.

Lecture 5 Cache Operation

Cache Memory Yi-Ning Huang. Principle of Locality Principle of Locality A phenomenon that the recent used memory location is more likely to be used again.

CSCI206 - Computer Organization & Programming

DREAM TEAM 2 Roto, Holiano, Chaka

CS2100 Computer Organization

Direct Cache Structure

Replacement Policy Replacement policy:

Memory Hierarchy Virtual Memory, Address Translation

Consider a Direct Mapped Cache with 4 word blocks

Paging Examples Assume a page size of 1K and a 15-bit logical address space. How many pages are in the system?

Exploiting Memory Hierarchy Chapter 7

CSCI206 - Computer Organization & Programming

FIGURE 12-1 Memory Hierarchy

Chapter 5 Memory CSE 820.

Set-Associative Cache

Interconnect with Cache Coherency Manager

Lecture 22: Cache Hierarchies, Memory

Help! How does cache work?

Direct Mapping.

Module IV Memory Organization.

10/16: Lecture Topics Memory problem Memory Solution: Caches Locality

CSCI 6307 Foundation of Systems – Exercise (3)

CS-447– Computer Architecture Lecture 20 Cache Memories

Basic Cache Operation Prof. Eric Rotenberg

Some of the slides are adopted from David Patterson (UCB)

Cache Memory and Performance

Lecture 13: Cache Basics Topics: terminology, cache organization (Sections )

Overview Problem Solution CPU vs Memory performance imbalance

Presentation transcript:

Tutorial Nine Cache CompSci 210 - Semester One 2016

Exercise 9.1 Answer the following questions for a direct-mapped cache with 8 cache lines, where each line has 1 word, each word is 2 bytes, and the address bus is 16 bits. How many bits are needed for the index field How many bits are there in the tag field How much data can be held in the cache

Exercise 9.1 Answer the following questions for a direct-mapped cache with 8 cache lines, where each line has 1 word, each word is 2 bytes, and the address bus is 16 bits. How many bits are needed for the index field How many bits are there in the tag field How much data can be held in the cache

Exercise 9.1 Answer the following questions for a direct-mapped cache with 8 cache lines, where each line has 1 word, each word is 2 bytes, and the address bus is 16 bits. How many bits are needed for the index field (3 bits) How many bits are there in the tag field How much data can be held in the cache

Exercise 9.1 Answer the following questions for a direct-mapped cache with 8 cache lines, where each line has 1 word, each word is 2 bytes, and the address bus is 16 bits. How many bits are needed for the index field (3 bits) How many bits are there in the tag field How much data can be held in the cache

Exercise 9.1 Answer the following questions for a direct-mapped cache with 8 cache lines, where each line has 1 word, each word is 2 bytes, and the address bus is 16 bits. How many bits are needed for the index field (3 bits) How many bits are there in the tag field (13 bits) How much data can be held in the cache

Exercise 9.1 Answer the following questions for a direct-mapped cache with 8 cache lines, where each line has 1 word, each word is 2 bytes, and the address bus is 16 bits. How many bits are needed for the index field (3 bits) How many bits are there in the tag field (13 bits) How much data can be held in the cache

Exercise 9.1 Answer the following questions for a direct-mapped cache with 8 cache lines, where each line has 1 word, each word is 2 bytes, and the address bus is 16 bits. How many bits are needed for the index field (3 bits) How many bits are there in the tag field (13 bits) How much data can be held in the cache (16 bytes)

Cache Trace Memory Access Slot # Address Item 1 2 3 4 5 6 7 Memory Access 0x4503, 0x450C, 0x4503, 0x452B, 0x5071, 0x450C, 0x45FE, 0x450C

Cache Trace Access 0x4503 Memory Access Slot # Address Item 1 2 3 4 5 6 7 Access 0x4503 Memory Access 0x4503, 0x450C, 0x4503, 0x452B, 0x5071, 0x450C, 0x45FE, 0x450C

Cache Trace Access 0x4503 0100 0101 0000 0011 Memory Access Slot # Address Item 1 2 3 4 5 6 7 Access 0x4503 0100 0101 0000 0011 Memory Access 0x4503, 0x450C, 0x4503, 0x452B, 0x5071, 0x450C, 0x45FE, 0x450C

Cache Trace Access 0x4503 0100 0101 0000 0011 Memory Access Slot # Address Item 1 2 3 4 5 6 7 Access 0x4503 0100 0101 0000 0011 Memory Access 0x4503, 0x450C, 0x4503, 0x452B, 0x5071, 0x450C, 0x45FE, 0x450C

Cache Trace Access 0x4503 Cache Miss! 0100 0101 0000 0011 Slot # Address Item 1 2 3 4 5 6 7 Access 0x4503 Cache Miss! 0100 0101 0000 0011 Memory Access 0x4503, 0x450C, 0x4503, 0x452B, 0x5071, 0x450C, 0x45FE, 0x450C

Cache Trace Access 0x4503 0100 0101 0000 0011 Memory Access Slot # Address Item 1 2 3 0x4503 4 5 6 7 Access 0x4503 0100 0101 0000 0011 Memory Access 0x4503, 0x450C, 0x4503, 0x452B, 0x5071, 0x450C, 0x45FE, 0x450C

Cache Trace Memory Access Slot # Address Item 1 2 3 0x4503 4 5 6 7 Memory Access 0x4503, 0x450C, 0x4503, 0x452B, 0x5071, 0x450C, 0x45FE, 0x450C

Cache Trace Access 0x450C Memory Access Slot # Address Item 1 2 3 0x4503 4 5 6 7 Access 0x450C Memory Access 0x4503, 0x450C, 0x4503, 0x452B, 0x5071, 0x450C, 0x45FE, 0x450C

Cache Trace Access 0x450C 0100 0101 0000 1100 Memory Access Slot # Address Item 1 2 3 0x4503 4 5 6 7 Access 0x450C 0100 0101 0000 1100 Memory Access 0x4503, 0x450C, 0x4503, 0x452B, 0x5071, 0x450C, 0x45FE, 0x450C

Cache Trace Access 0x450C 0100 0101 0000 1100 Memory Access Slot # Address Item 1 2 3 0x4503 4 5 6 7 Access 0x450C 0100 0101 0000 1100 Memory Access 0x4503, 0x450C, 0x4503, 0x452B, 0x5071, 0x450C, 0x45FE, 0x450C

Cache Trace Access 0x450C Cache Miss! 0100 0101 0000 1100 Slot # Address Item 1 2 3 0x4503 4 5 6 7 Access 0x450C Cache Miss! 0100 0101 0000 1100 Memory Access 0x4503, 0x450C, 0x4503, 0x452B, 0x5071, 0x450C, 0x45FE, 0x450C

Cache Trace Access 0x450C 0100 0101 0000 1100 Memory Access Slot # Address Item 1 2 3 0x4503 4 0x450C 5 6 7 Access 0x450C 0100 0101 0000 1100 Memory Access 0x4503, 0x450C, 0x4503, 0x452B, 0x5071, 0x450C, 0x45FE, 0x450C

Cache Trace Access 0x4503 Memory Access Slot # Address Item 1 2 3 0x4503 4 0x450C 5 6 7 Access 0x4503 Memory Access 0x4503, 0x450C, 0x4503, 0x452B, 0x5071, 0x450C, 0x45FE, 0x450C

Cache Trace Access 0x4503 Cache Hit! Memory Access Slot # Address Item 1 2 3 0x4503 1, 3 4 0x450C 5 6 7 Access 0x4503 Cache Hit! Memory Access 0x4503, 0x450C, 0x4503, 0x452B, 0x5071, 0x450C, 0x45FE, 0x450C

Cache Trace Access 0x452B Memory Access Slot # Address Item 1 2 3 0x4503 1, 3 4 0x450C 5 6 7 Access 0x452B Memory Access 0x4503, 0x450C, 0x4503, 0x452B, 0x5071, 0x450C, 0x45FE, 0x450C

Cache Trace Access 0x452B Cache Miss! 0100 0101 0010 1011 Slot # Address Item 1 2 3 0x4503 1, 3 4 0x450C 5 6 7 Access 0x452B Cache Miss! 0100 0101 0010 1011 Memory Access 0x4503, 0x450C, 0x4503, 0x452B, 0x5071, 0x450C, 0x45FE, 0x450C

Cache Trace Access 0x5071 Memory Access Slot # Address Item 1 2 3 0x452B 4 0x450C 5 6 7 Access 0x5071 Memory Access 0x4503, 0x450C, 0x4503, 0x452B, 0x5071, 0x450C, 0x45FE, 0x450C

Cache Trace Access 0x5071 Cache Miss! Memory Access Slot # Address Item 1 0x5071 5 2 3 0x452B 4 0x450C 6 7 Access 0x5071 Cache Miss! Memory Access 0x4503, 0x450C, 0x4503, 0x452B, 0x5071, 0x450C, 0x45FE, 0x450C

Cache Trace Access 0x450C Cache Hit! Memory Access Slot # Address Item 1 0x5071 5 2 3 0x452B 4 0x450C 2, 6 6 7 Access 0x450C Cache Hit! Memory Access 0x4503, 0x450C, 0x4503, 0x452B, 0x5071, 0x450C, 0x45FE, 0x450C

Cache Trace Access 0x45FE Cache Miss! Memory Access Slot # Address Item 1 0x5071 5 2 3 0x452B 4 0x450C 2, 6 6 0x45FE 7 Access 0x45FE Cache Miss! Memory Access 0x4503, 0x450C, 0x4503, 0x452B, 0x5071, 0x450C, 0x45FE, 0x450C

Cache Trace Access 0x450C Cache Hit! Memory Access Slot # Address Item 1 0x5071 5 2 3 0x452B 4 0x450C 2, 6, 8 6 0x45FE 7 Access 0x450C Cache Hit! Memory Access 0x4503, 0x450C, 0x4503, 0x452B, 0x5071, 0x450C, 0x45FE, 0x450C