Topics Design rules and fabrication SCMOS scalable design rules

Slides:



Advertisements
Similar presentations
Static CMOS Circuits.
Advertisements

CMOS Process at a Glance
VLSI Design Lecture 2: Basic Fabrication Steps and Layout
EE213 VLSI DesignStephen Daniels 2003 VLSI Design Design Rules EE213 VLSI Design.
Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE VLSI Circuit Design Lecture 4 - Layout &
Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Topics n Basic fabrication steps n Transistor structures n Basic transistor behavior.
Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.
Lecture #51 Lecture #5 – VLSI Design Review zPhotolithography zPatterning Silicon zProcess steps used are: yStarts with Si wafer yThermal oxidation yPhotoresist.
CSE477 L05 IC Manufacturing.1Irwin&Vijay, PSU, 2002 CSE477 VLSI Digital Circuits Fall 2002 Lecture 05: IC Manufacturing Mary Jane Irwin (
CMOS Fabrication Details
Module-3 (MOS designs,Stick Diagrams,Designrules)
Ch.8 Layout Verification TAIST ICTES Program VLSI Design Methodology Hiroaki Kunieda Tokyo Institute of Technology.
2. Transistors and Layout Fabrication techniques Transistors and wires Design rule for layout Basic concepts and tools for Layout.
Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 LECTURE : KEEE 4425 WEEK 6/2 DESIGN RULES,LAYOUT AND STICK DIAGRAM.
Design Rules EE213 VLSI Design.
Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Topics n Basic fabrication steps. n Transistor structures. n Basic transistor behavior.
Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Topics n Design rules and fabrication. n SCMOS scalable design rules. n Stick.
Topics SCMOS scalable design rules. Reliability. Stick diagrams. 1.
ECE484: Digital VLSI Design Fall 2010 Lecture: IC Manufacturing
Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-1 Lecture 10 Wire and Via Jan. 27, 2003.
STICK DIAGRAM EMT251. Schematic vs Layout In Out V DD GND Inverter circuit.
CMOS Fabrication nMOS pMOS.
VLSI Design Lecture 3: Parasitics of CMOS Wires Mohammad Arjomand CE Department Sharif Univ. of Tech. Adapted with modifications from Harris’s lecture.
Topics Basic fabrication steps. Transistor structures.
NMOS FABRICATION 1. Processing is carried out on a thin wafer cut from a single crystal of silicon of high purity into which the required p-impurities.
Purpose of design rules:
Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Topics n Basic fabrication steps n Transistor structures n Basic transistor behavior.
1 Overview of Fabrication Processes of MOSFETs and Layout Design Rules.
Dynamic Behavior of MOS Transistor. The Gate Capacitance t ox n + n + Cross section L Gate oxide x d x d L d Polysilicon gate Top view Gate-bulk overlap.
CMOS VLSI Fabrication.
STICK DIAGRAM EMT251. Schematic vs Layout In Out V DD GND Inverter circuit.
Layout design rules. 2 Introduction  Layout rules is also referred as design rules.  It is considered as a prescription for preparing photomasks. 
EE141 Manufacturing 1 Chapter 2 Manufacturing Process and CMOS Circuit Layout 1 st rev. : March 7, nd rev. : April 10, 2003.
Stick Diagrams Stick Diagrams electronics.
UNIT II CIRCUIT DESIGN PROCESSES
EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated.
Out Line of Discussion on VLSI Design Basics
Patterning - Photolithography
CSE477 L05 IC Manufacturing.1Irwin&Vijay, PSU, 2003 CSE477 VLSI Digital Circuits Fall 2003 Lecture 05: IC Manufacturing Mary Jane Irwin (
Full-Custom Design ….TYWu
Full-Custom Design …. TYWu. Outline Introduction Transistor Process Steps Layout Schematic R/C Design Rules Tools.
S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
IC Manufactured Done by: Engineer Ahmad Haitham.
Layout of CMOS Circuits
Subject Name: Fundamentals Of CMOS VLSI Subject Code: 10EC56
Manufacturing Process I
Geometric Design Rules
Layout and fabrication of CMOS circuits
Chapter 1 & Chapter 3.
Chapter 4 Interconnect.
Topics Basic fabrication steps. Transistor structures.
VLSI Design MOSFET Scaling and CMOS Latch Up
EE213 VLSI DesignStephen Daniels 2003 VLSI Design Design Rules EE213 VLSI Design.
Design Rules.
Digital Integrated Circuits A Design Perspective
Chapter 10: IC Technology
Lecture #25 OUTLINE Device isolation methods Electrical contacts to Si
Introduction to Layout Inverter Layout Example Layout Design Rules
LAYOUT DESIGN RULES Bellary Engg College,Bellary, karnataka
Manufacturing Process I
VLSI Lay-out Design.
VLSI Design CMOS Layout
V.Navaneethakrishnan Dept. of ECE, CCET
Chapter 10: IC Technology
ECE 424 – Introduction to VLSI Design
Manufacturing Process I
CMOS Layers n-well process p-well process Twin-tub process.
Chapter 10: IC Technology
Presentation transcript:

Topics Design rules and fabrication SCMOS scalable design rules Stick diagrams 1

Why we need design rules Masks are tooling for manufacturing. Manufacturing processes have inherent limitations in accuracy. Design rules specify geometry of masks which will provide reasonable yields. Design rules are determined by experience.

Manufacturing problems Photoresist shrinkage, tearing. Variations in material deposition. Variations in temperature. Variations in oxide thickness. Impurities. Variations between lots. Variations across a wafer.

Transistor problems Variations in threshold voltage: oxide thickness; ion implantation; poly variations. Changes in source/drain diffusion overlap. Variations in substrate.

Wiring problems Diffusion: changes in doping -> variations in resistance, capacitance. Poly, metal: variations in height, width -> variations in resistance, capacitance. Shorts and opens:

Oxide problems Variations in height. Lack of planarity -> step coverage. metal 2 metal 2 metal 1

Via problems Via may not be cut all the way through. Undersize via has too much resistance. Via may be too large and create short.

 and design rules  is the size of a minimum feature. Specifying  particularizes the scalable rules. Parasitics are generally not specified in units

MOSIS SCMOS design rules Designed to scale across a wide range of technologies. Designed to support multiple vendors. Designed for educational use. Ergo, fairly conservative.

Wires metal 3 6 metal 2 3 metal 1 3 pdiff/ndiff 3 poly 2

Transistors 2 2 3 3 1 5

Vias Types of via: metal1/diff, metal1/poly, metal1/metal2. 4 4 1 2

Tub tie 4 1

Spacings Diffusion/diffusion: 3 Poly/poly: 2 Poly/diffusion: 1 Via/via: 2 Metal1/metal1: 3 Metal2/metal2: 4 Metal3/metal3: 4

Stick diagrams A stick diagram is a cartoon of a layout. Does show all components/vias (except possibly tub ties), relative placement. Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.

Stick layers metal 3 metal 2 metal 1 poly ndiff pdiff

Dynamic latch stick diagram VDD in out VSS phi phi

Layout design and analysis tool Layout editor Design rule checker (DRC) Circuit extractor 1