V. Tocut, LAL/IN2P3 Orsay H. Lebbolo LPNHE/IN2P3 Paris

Slides:



Advertisements
Similar presentations
DAQ WS03 Sept 2006Jean-Sébastien GraulichSlide 1 Report on FEE for PID o Reminder o TOF o EMCAL o Summary Jean-Sebastien Graulich, Geneva.
Advertisements

TOF Front End electronics
SiLC Front-End Electronics LPNHE Paris March 15 th 2004.
TOF Electronics Qi An Fast Electronics Lab, USTC Sept. 16~17, 2002.
AIDA design review Davide Braga Steve Thomas ASIC Design Group 9 June 2009.
Second generation Front-end chip for H-Cal SiPM readout : SPIROC DESY Hamburg – le 13 février 2007 M. Bouchel, F. Dulucq, J. Fleury, C. de La Taille, G.
MR (7/7/05) T2K electronics Beam structure ~ 8 (9?) bunches / spill bunch width ~ 60 nsec bunch separation ~ 600 nsec spill duration ~ 5  sec Time between.
A. Rivetti Gigatracker meeting, dec 2009 Charge measurement with the TDC per pixel architecture A. Rivetti, G. Dellacasa S. Garbolino, F. Marchetto, G.
QIE10 Issues Tom Zimmerman Fermilab Oct. 28,
Large area photodetection for Water Cerenkov detectors PMm 2 proposal: Front End Electronics MAROC ASIC Pierre BARRILLON, Sylvie BLIN, Jean-Eric CAMPAGNE,
L.ROYER – TWEPP Oxford – Sept The chip Signal processing for High Granularity Calorimeter (Si-W ILC) L.Royer, J.Bonnard, S.Manen, X.Soumpholphakdy.
HINP32C Southern Illinois University Edwardsville VLSI Design Research Laboratory Washington University in Saint Louis Nuclear Reactions Group.
McGill Increasing the Time Dynamic Range of Pulse Measurement Techniques in Digital CMOS Applications of Pulse Measurement: Duty-Cycle Measurement Pulsed.
L.Royer– Calice LLR – Feb Laurent Royer, J. Bonnard, S. Manen, P. Gay LPC Clermont-Ferrand R&D pole MicRhAu dedicated to High.
SPIROC update Felix Sefkow Most slides from Ludovic Raux HCAL main meeting April 18, 2007.
Single tube detection efficiency BIS-MDT GARFIELD Simulation GARFIELD Simulation Anode wire voltage as a function of the distance from the wire Electric.
Jean-François Genat Fast Timing Workshop June 8-10th 2015 FZU Prague Timing Methods with Fast Integrated Technologies 1.
SKIROC ADC measurements and cyclic ADC LPC Clermont-Ferrand Laurent ROYER, Samuel MANEN Calice/Eudet electronic meeting Orsay June.
Click to edit Master subtitle style Presented By Mythreyi Nethi HINP16C.
S. Bota – Calorimeter Electronics overview - July 2002 Status of SPD electronics Very Front End Review of ASIC runs What’s new: RUN 4 and 5 Next Actions.
Juin 1st 2010 Christophe Beigbeder PID meeting1 PID meeting Electronics Integration.
Mai 31th 2011 Christophe Beigbeder PID meeting1 ETD meeting Test setup : Activities in Bari, Univ of Maryland and at Orsay Test setup : Activities in Bari,
PArISROC Photomultiplier Array Integrated in Sige Read Out Chip Selma Conforti Frédéric Dulucq Christophe de La Taille Gisèle Martin-Chassard Wei
1 D. BRETON 1, L.LETERRIER 2, V.TOCUT 1, Ph. VALLERAND 2 (1) LAL ORSAY - France (2) LPC CAEN - France Super Nemo Absolute Time Stamper A high resolution.
C.Beigbeder, D.Breton, M.El Berni, J.Maalmi, V.Tocut – LAL/In2p3/CNRS L.Leterrier, S. Drouet - LPC/In2p3/CNRS P. Vallerand - GANIL/CNRS/CEA SuperB -Collaboration.
Ongoing work on ASIC development at Politecnico-Bari F. Corsi, F. Ciciriello, F. Licciulli, C. Marzocca, G. Matarrese DEE - Politecnico di Bari and INFN.
ASAD Workshop Saclay (CEA Irfu) November 25, AGET circuit: Application Information actar.
Silicon Tracker Data Acquisition and Electronics for the Linear Collider Jean-Francois Genat LPNHE Universite Pierre et Marie Curie CNRS/IN2P3 On behalf.
The design of fast analog channels for the readout of strip detectors in the inner layers of the SuperB SVT 1 INFN Sezione di Pavia I Pavia, Italy.
End OF Column Circuits – Design Review
"North American" Electronics
STATUS OF SPIROC measurement
DCH FEE STATUS Level 1 Triggered Data Flow FEE Implementation &
ETD meeting Architecture and costing On behalf of PID group
Front-end Electronic for a neutrino telescope : a new ASIC SCOTT
Journées VLSI-FPGA-PCB Juin 2010 Xiaochao Fang
Jinfan Chang Experimental Physics Center , IHEP Feb 18 , 2011
A General Purpose Charge Readout Chip for TPC Applications
Christophe Beigbeder PID meeting
ASIC PMm2 Pierre BARRILLON, Sylvie BLIN, Selma CONFORTI,
ETD meeting First estimation of the number of links
on behalf of the AGH and UJ PANDA groups
Timing and fast analog memories in Saclay
Integrated Circuits for the INO
Designing electronics for a TOF Forward PID for SuperB D. Breton & J
ETD meeting Electronic design for the barrel : Front end chip and TDC
From SNATS to SCATS C. Beigbeder1, D. Breton1,F.Dulucq1, L. Leterrier2, J. Maalmi1, V. Tocut1, Ph. Vallerand3 1 : LAL Orsay, France (IN2P3 – CNRS) 2 :
PID meeting SCATS Status on front end design
Christophe Beigbeder PID meeting
DCH FEE 28 chs DCH prototype FEE &
L. Ratti, M. Manghisoni Università degli Studi di Pavia INFN Pavia
Jean-Francois Genat LPNHE Universite Pierre et Marie Curie CNRS/IN2P3
Front-end electronics Bis7-8
R&D on large photodetectors and readout electronics FJPPL KEK/Orsay JE Campagne, S. Conforti, F. Dulucq, C. de La Taille, G. Martin-Chassard,, A.
MCPPMT test bench at LAL D. Breton, L. Burmistov, J. Maalmi, V
FIT Front End Electronics & Readout
TDC at OMEGA I will talk about SPACIROC asic
Christophe Beigbeder PID meeting
A Low Power Readout ASIC for Time Projection Chambers in 65nm CMOS
Christophe Beigbeder/ ETD PID meeting
Christophe de La Taille * Gisèle Martin-Chassard *
TPC electronics Atsushi Taketani
PID electronics for FDIRC (Focusing Detector of Internally Reflected Cherenkov light) and FTOF (Forward Time of Flight) Christophe Beigbeder and Dominique.
Presented at 2016 IEEE Nuclear Science Symposium - N28-32
Signal processing for High Granularity Calorimeter
V. Tocut, LAL/IN2P3 Orsay H. Lebbolo LPNHE/IN2P3 Paris
1INFN Sez. Bari, 2Università degli Studi di Bari “A. Moro”
Presented by T. Suomijärvi
Electronics for the PID
Orsay Talks Christophe : General questions and future developments.
Presentation transcript:

V. Tocut, LAL/IN2P3 Orsay H. Lebbolo LPNHE/IN2P3 Paris PId Front End Chip: PIF V. Tocut, LAL/IN2P3 Orsay H. Lebbolo LPNHE/IN2P3 Paris

H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 04/2011 Requirement reminder Time measurement : 100ps resolution max Considering 70ps TDC resolution 1MHz background rate max 50ns double pulse resolution min Charge measurement : dynamic range of 10 8 bits run always H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 04/2011

H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 04/2011 Charge Measurement Charge measurements will improve the resolution H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 04/2011

PIF: Babar like FE chip  ‘Constant Fraction Discriminator’ like *16 Charge measurement To ADC IN 16 Low walk discriminator To TDC H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 04/2011

H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 04/2011 PIF: Babar like FE chip +++ No walk correction if walk < 50ps (depending on PM dynamics) Charge measurement to improve resolution --- Need « Time + charge » data synchronization 2 different chips developed: analog front end -> {PIF }: CFD like and charge measurement  time measurement -> {SCATS} H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 04/2011

H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 04/2011 PIF proposal Charge Amplifier Mux State Machine Charge output (To ADC) Pseudo CFD Synchronization with TDC data To TDC In00 Sample & Hold H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 04/2011

H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 04/2011 CFD on silicon Fast comparator  Fast comparator Classical CFD Proposed pseudo CFD Delay + Fraction  Gain + Integrators H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 04/2011

H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 04/2011 Spice Simulations H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 04/2011

H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 04/2011 CFD Implementation Threshold DAC Reset PM Fast Comparator Amplifier outp LVDS D flip flop D Delay / Filter Fast Comparator C outn Amplifier Charge Amplifier To ADC H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 04/2011

Simulations with AMS CMOS 0.35µ H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 04/2011

Simulations with AMS CMOS 0.35µ Difference between amplified signal and delayed amplified signal H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 04/2011

Parametric simulation : amplitude from 1 to 100 70ps walk Resolution: 70ps for a dynamic of 100 100ps total resolution H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 04/2011

Parametric simulation : amplitude from 1 to 10 45ps walk Resolution: 50ps for a dynamic of 100 86ps total resolution H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 04/2011

H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 04/2011 Milestones PIF the Chip : Design & Simulations with CMOS AMS 0.35µ Submission by the end of 2011 H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 04/2011

V. Tocut, LAL/IN2P3 Orsay H. Lebbolo LPNHE/IN2P3 Paris CRT Test Bench FE V. Tocut, LAL/IN2P3 Orsay H. Lebbolo LPNHE/IN2P3 Paris

H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 04/2011 CRT Test Bench Up to 16 channels on Discri mezzanine Several architecture could be implemented: Classical CFD and Charge Amp Channel Simple discri and Charge Amp Channel PIF-like CFD and Charge Amp Channel H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 04/2011

Classical CFD and Charge Amp Channel H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 04/2011

Simple discri and Charge Amp Channel H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 04/2011

PIF-like CFD and Charge Amp Channel H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 04/2011