Subject Name: FUNDAMENTALS OF HDL Subject Code: 10EC45 Prepared By: DIVYA P K Department: ELECTRONICS AND COMMUNICATION Date: 26-02-2015 5/17/2018

Hardware Description Language - Introduction HDL is a language that describes the hardware of digital systems in a textual form. It resembles a programming language, but is specifically oriented to describing hardware structures and behaviors. The main difference with the traditional programming languages is HDL’s representation of extensive parallel operations whereas traditional ones represents mostly serial operations. The most common use of a HDL is to provide an alternative to schematics. 5/17/2018

– VHDL (VHSIC (Very High Speed Integrated Circuits) Most popular HDLs are – VHDL (VHSIC (Very High Speed Integrated Circuits) HDL – Developed for the U. S. DOD. – Verilog® – Developed by Gateway Design Automation, which was bought by Cadence® Design Systems. . 5/17/2018

VHDL (VHSIC (Very High Speed Integrated Circuits) VHDL is the most common Large standard developed by US DoD VHDL = VHSIC HDL VHSIC = Very High Speed Integrated Circuit 5/17/2018

VERILOG HDL Verilog HDL is second most common Easier to use in many ways = better for teaching C - like syntax History Developed as proprietary language in 1985 Opened as public domain spec in 1990 Due to losing market share to VHDL Became IEEE standard in 1995 5/17/2018

STRUCTURE OF DATA FLOW DESCRIPTION LIBRARY declarations: Contains a list of all libraries to be used in the design. For Example: ieee, std, work, etc. ENTITY: Specifies the I/O pins of the circuit. ARCHITECTURE: Contains the VHDL code, which describes how the circuit should behave (function). 5/17/2018

VHDL PORTS in input port. A variable or a signal can read a value from a port of mode in, but is not allowed to assign a value to it. out output port. It is allowed to make signal assignments to a port of the mode out, but it is not legal to read from it. inout bi-directional port. Both assignments to such a port and reading from it are allowed. buffer output port with read capability. It differs from inout in that it can be updated by at most one source, whereas inout can be updated by zero or more sources. linkage . The value of the port may be read or updated, but only by appearing as an actual corresponding to an interface object of mode linkage. 5/17/2018

MODULES Let’s start to consider systems without hierarchy (no submodules) A module contains objects declarations and concurrent processes that operate in parallel. Initial blocks Always blocks Continuous assignments (instantiations of submodules) 5/17/2018

VERILOG PORTS in input port. A variable or a signal can read a value from a port of mode in, but is not allowed to assign a value to it. out output port. It is allowed to make signal assignments to a port of the mode out, but it is not legal to read from it. inout bi-directional port. Both assignments to such a port and reading from it are allowed. 5/17/2018 5/17/2018

OPERATORS TYPES 5/17/2018 5/17/2018

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DATA TYPES Scalar Data Types (Built into VHDL) - scalar means that the type only has one value at any given time Boolean - values {TRUE, FALSE} - not the same as '0' or '1' Character - values are all symbols in the 8-bit ISO8859-1 set (i.e., Latin-1) - examples are '0', '+', 'A', 'a', '\' Integer - values are whole numbers from -2,147,483,647 to +2,147,483,647 - the range comes from +/- 232 - examples are -12, 0, 1002 Real - values are fractional numbers from -1.0E308 to +1.0E308 - examples are 0.0, 1.134, 1.0E5 Bit - values {'0', '1'} - different from Boolean - this type can be used for logic gates - single bits are always represented with single quotes (i.e., '0', '1') Scalar Data Types (Built into VHDL) - scalar means that the type only has one value at any given time Boolean - values {TRUE, FALSE} - not the same as '0' or '1' Character - values are all symbols in the 8-bit ISO8859-1 set (i.e., Latin-1) - examples are '0', '+', 'A', 'a', '\' Integer - values are whole numbers from -2,147,483,647 to +2,147,483,647 - the range comes from +/- 232 - examples are -12, 0, 1002 Real - values are fractional numbers from -1.0E308 to +1.0E308 - examples are 0.0, 1.134, 1.0E5 Bit - values {'0', '1'} - different from Boolean - this type can be used for logic gates - single bits are always represented with single quotes (i.e., '0', '1') 5/17/2018

DATA TYPES Array Data Types (Built into VHDL) - array is a name that represents multiple signals Bit_Vector - vector of bits, values {'0', '1'} - array values are represented with double quotes (i.e., "0010") - this type can be used for logic gates ex) Addr_bus : in BIT_VECTOR (7 downto 0); - unlimited range - first element of array has index=0 (i.e., Addr_bus(0)…) String - vector of characters, values{Latin-1} - again use double quotes - define using "to" or "downto" ("to" is easier for strings) ex) Message : string (1 to 10) := "message here…" - first element in array has index=1, this is different from BIT_VECTOR 5/17/2018

DATA TYPES Physical Data Types (Built into VHDL) - these types contain object value and units - NOT synthesizable Time - range from -2,147,483,647 to +2,147,483,647 - units: fs, ps, ns, us, ms, sec, min, hr User-Defined Enumerated Types - we can create our own descriptive types, useful for State Machine - no quotes needed ex) type States is (Red, Yellow, Green); 5/17/2018

STD_LOGIC Data Types STD_LOGIC - we talked about the need for realistic data types to model busses and drive strength - within VHDL we only have BIT and BIT_VECTOR to model logic gates - these don't work for the real world - we need to use the IEEE.STD_LOGIC_1164.ALL package STD_LOGIC - "resolved" data type, scalar (analogous to BIT, but with drive strength) STD_LOGIC_VECTOR - "resolved" data type, vector (analogous to BIT_VECTOR, but with drive strength) - we use this package by entering the following: library IEEE; use IEEE.STD_LOGIC_1164.ALL 5/17/2018

STD_LOGIC Data Types Resolution - These types have the following possible values U = Un-Initialized X = Forcing Unknown 0 = Forcing '0' 1 = Forcing '1' Z = Forcing 'Z' W = Weak Unknown L = Weak '0' H = Weak '1' - = Don't Care - There is a table that VHDL can go to in order to "Resolve" any of the following conditions on a single line ex) 0 and H = 0 0 and 1 = 0 - we will always use these data types (from now on, don't use BIT or BIT_VECTOR) 5/17/2018

Structural Description – This is directly equivalent to the schematic of a circuit and is specifically oriented to describing hardware structures using the components of a circuit. Dataflow Description – This describes a circuit in terms of function rather than structure and is made up of concurrent assignment statements or their equivalent. Concurrent assignments statements are executed concurrently, i.e. in parallel whenever one of the values on the right hand side of the statement changes. Behavioral description- The Behavioral VHDL module describes features of the language that describe the behavior of components in response to signals. Behavioral descriptions of hardware utilize software engineering practices and constructs to achieve a functional model. Timing information is not necessary in a behavioral description, although such information may be included easily. 5/17/2018

Styles (Types) of Description Behavioral Description entity half_add is port (I1, I2 : in bit; O1, O2 : out bit); end half_add ; architecture behave_ex of half_add is --The architecture consists of a process construct begin process (I1, I2) --The above statement is process statement O1 <= I1 xor I2 after 10 ns ; O2 <= I1 and I2 after 10 ns;   end process; end behave_ex; 5/17/2018

port (a, b : in std_logic; sum, cout : out std_logic); end system; STRUCTURAL entity system is port (a, b : in std_logic; sum, cout : out std_logic); end system; architecture struct_exple of system is component xor2 --The above statement is a component statement port(I1, I2 : in std_logic; O1 : out std_logic); end component; component and2 begin X1: xor2 port map (a,b, sum); A1: and2 port map (a,b, cout); end struct_exple; 5/17/2018

Switch-Level Description entity Inverter is Port (y : out std_logic; a: in std_logic );--VHDL does not have built-in switch-level end Inverter; architecture Invert_switch of Inverter is component nmos --nmos is one of the key words for switch-level. port (O1: out std_logic; I1, I2 : in std_logic); end component; ………….. for all: pmos use entity work. mos (pmos_behavioral); for all: nmos use entity work. mos (nmos_behavioral); --The above two statements are referring to a package mos --See details in Chapter 5 constant vdd: std_logic := '1'; constant gnd : std_logic:= '0'; begin p1 : pmos port map (y, vdd, a); n1: nmos port map (y, gnd, a); end Invert_switch; 5/17/2018

architecture HA_DtFl of halfadder is Data Flow Description entity halfadder is port ( a: in bit; b: in bit; s: out bit; c: out bit); end halfadder; architecture HA_DtFl of halfadder is --The architecture has no process, component, cmos, --tranif0, tran,or tranif0 begin s <= a xor b; c <= a and b; end HA_DtFl; 5/17/2018

Two Models for VHDL Programs • Two models • Simulation – Describe the behavior of the circuit in terms of input signals, the output signals, knowledge of delays – Behavior described in terms of occurrences of events and waveforms on signals • Synthesis – Reverse process – inference of hardware from description – The synthesis tool will infer a hardware architecture from the VHDL model – When writing a VHDL program, think of the hardware that synthesis tool would infer from it 5/17/2018

DIFFERENCE BETWEEN VHDL AND VERILOG DATA TYPES Type oriented language User defined type Can handle multidimensional array types Ease of learning Hard to learn because of its rigid type requirements Libraries and packages Can be attached to Standard VHDL packages Operators VHDL Operators does not have predefined Unary Operators Procedures and Tasks VHDL allows a function to be written inside the procedures body DATA TYPES All type defined by language Not User defined type Can not handle multidimensional array types Ease of learning User just write the module without worrying about what library or package should be obtained Libraries and packages There is a no concept of Libraries and packages Operators VHDL Operators have predefined Unary Operators Procedures and Tasks Functions are not allowed to be written inside the task’s body 5/17/2018