Digital System Design An Introduction to Verilog® HDL

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Presentation transcript:

Digital System Design An Introduction to Verilog® HDL Sharif University of Technology Department of Computer Engineering Digital System Design An Introduction to Verilog® HDL Alireza Ejlali

Verilog HDL Textbook A guide to Digital Design and Synthesis Samir Palnitkar SunSoft Press 1996

Hardware Description Languages HDL Popular HDLs (IEEE Standard) Verilog® =Verifying Logic VHDL Other HDLs AHPL TI-HDL AHDL Basic Idea Programming Languages

HDL Requirements Concurrency Timing Support for Design Hierarchy Structural Specification Pragmatics

Applications Communication Documentation Computer Aided Design (CAD) Human / Computer Human / Human Documentation Computer Aided Design (CAD) Simulation Synthesis

Why are HDLs essential? SSI (Small Scale Integration) MSI (Medium Scale Integration) Paper and Pencil LSI (Large Scale Integration) ASM (Algorithmic State Machine) VLSI (Very Large Scale Integration) CAD (HDLs)

Verilog VS. VHDL VHDL Verilog More general language Not all constructs are synthesizable Verilog Not as general as VHDL Most constructs are synthesizable

Design Flow Design specification Behavioral description RTL description Functional verification and testing Logic synthesis Gate-level netlist Logical verification and testing Floor planning, automatic place & route Physical layout Layout verification Implementation

Popularity of Verilog HDL Easy to learn, Easy to write Similar in Syntax to C Allows different levels of abstraction and mixing them Supported by most popular CAD tools and vendors PLI to customize Verilog simulators to designers’ needs

Design Methodologies