سبکهاي طراحي (Design Styles)
Cell-based (Std-cell, Macrocell) Array-based (MPGA-FPGA) سبکهاي طراحي Performance Semi-custom Cell-based (Std-cell, Macrocell) Array-based (MPGA-FPGA)
Full-Custom
Full-Custom Design Layout editors Very compact chip Highly optimized electrical properties Laborious efforts Layout editors Error-prone Relative lack of automation Useful for microprocessors/FPGAs High cost of design efforts Huge volumes Strict Performance/area/… constraints
Standard Cell Design Vdd Vdd IN2 IN2 IN1 OUT OUT IN1 IN1 OUT IN2 GND Contact Metal layer Vdd IN2 Poly layer IN2 IN1 OUT OUT Diffusion layer IN1 p-type transistor IN1 OUT IN2 GND n-type transistor GND
Standard Cell Channelled vs, Channelless.
Layout with Macrocells Simple: A few standard-cells Complex: Embedded processor Memory block
Top-Level Assembly RAM/ROM Row based Control Logic Row based CPU
Gate Array
Uncommitted Gate Array
Committed Gate Array
Gate Array and Sea-of-Gates Channeled gate arrays: Cells arranged in rows Space left between routing Channel-less gate arrays: aka sea-of-gates Cells cover the entire chip Routing done over the unused devices
Structured ASIC Customized using only metallization layers Came in 2003 Like channel-less gate arrays Similarity: Customized using only metallization layers Reduces time and cost of generating remaining masks used to complete the device Difference: More complex tiles (LUT, MUX, …) Most of metallization layers are predefined Lower performance and higher power (than standard cell) but better than GA
Field Programmable Gate Array (FPGA)
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Field Programmable Gate Array (FPGA)
FPGA Placement & Routing
Field Programmable Gate Array (FPGA)
Comparison of Design Styles Macrocell
Comparison of Design Styles Macrocell