The DEPFET for the ILC Vertex Detector 9/10/2018 The DEPFET for the ILC Vertex Detector Mannheim University Bonn University: R. Kohrs, M. Karagounis, H. Krüger, L. Reuen, C. Sandow, M. Trimpl, N. Wermes Mannheim University: P. Fischer, F. Giesen, I. Peric MPI Munich, HLL: L. Andricek, G. Lutz, H. G. Moser, R. H. Richter, M. Schnecke, and K. Heinzinger, P. Lechner, L. Strüder, J. Treis for the XEUS group at the HLL July, 2005 Ladislav Andricek, MPI für Physik, HLL Ladislav Andricek, MPI Munich

Outline Main Components System Performance Module Concept DEPFET Principle, Technology, Single pixel results, Radiation tolerance Steering chip SWITCHER II Read out chip CURO II System Performance on the test bench in the test beam at DESY Module Concept Material budget Power dissipation Thinning Technology Conclusion, what next?? July, 2005 Ladislav Andricek, MPI für Physik, HLL

DEPFET Principle Source Drain Gate internal amplification 9/10/2018 DEPFET Principle Source Drain Gate internal amplification no interconnection strays readout on demand non-destructive readout » unit cell of an Active Pixel Sensor » integrated readout device of SDD, CCD, … July, 2005 Ladislav Andricek, MPI für Physik, HLL Ladislav Andricek, MPI Munich

PXD4 - DEPFET: Two projects on one wafer XEUS ILC purpose imaging spectroscopy particle tracking sensor size 7.68 x 7.68 cm² 1.3 x 10 cm², 2.2 x 12.5 cm² pixel size 75 µm 25 µm sensor thickness 300 ... 500 µm 50 µm noise 4 el. ENC ~ 100 el. ENC Readout time per row 2.5 µs 20 ns July, 2005 Ladislav Andricek, MPI für Physik, HLL

cut perpendicular to channel (with clear) 9/10/2018 DEPFET Technology cut perpendicular to channel (with clear) July, 2005 Ladislav Andricek, MPI für Physik, HLL Ladislav Andricek, MPI Munich

DEPFET Technology micrograph of the latest production 9/10/2018 DEPFET Technology micrograph of the latest production (128x64 pixel, double pixel cell 33 x 47 µm2) Summary of PXD-04 production Test diodes/MOS-C (fully depleted 450 μm) Vdep = 30..40 V and 130..150 V Ivol = 100..200 pA/cm2 Isurf = 1.4 nA/cm2 Vfb = -1 V Technology extended to double poly/double metal and excellent bulk and surface properties preserved ! July, 2005 Ladislav Andricek, MPI für Physik, HLL Ladislav Andricek, MPI Munich

DEPFET Basic Parameters Transfer characteristics: subthreshold char. (W = 120µm L = 10µm) - drain current (μA) - drain current (nA) gate voltage(V) gate voltage(V) Output characteristics: drain current (A) Vth ≈ 0V subthreshold slope ≈ 80mV/dec Transistors can completely be turned off all basic parameters agree with simulations (W = 120µm L = 5µm) drain voltage(V) July, 2005 Ladislav Andricek, MPI für Physik, HLL

Internal Amplification transconductance of the internal gate time IDrain ion. drain current readout time cont. shaping, t=10 μs effective channel length L (mm) gq (pA/e-) measured value Simulation simple MOSFET model July, 2005 Ladislav Andricek, MPI für Physik, HLL

Gate Dielectrics 180 nm SiO2 + 30 nm Si3N4 Radiation Effects Gate Dielectrics 180 nm SiO2 + 30 nm Si3N4 1. postive oxide charge and postively charged oxide traps have to be compensated by a more negative gate voltage: negative shift of the theshold voltage 2. increased density of interface traps: higher 1/f noise and reduced mobility (gm) July, 2005 Ladislav Andricek, MPI für Physik, HLL

Threshold voltage shift GSF – National Research Center for Environment and Health, Munich 60Co (1.17 MeV and 1.33 MeV) CaliFa Teststand at MPI HLL X-Ray tube with Mo target at 30kV bremsstrahlung with peak at 17.44 keV 24 h annealing after each irradiation period  ~1 week irradiation annealing 3.5h 123.5h 293.5h "OFF" "ON" -∆Vth (V) ∆Not (cm-2) Dose (krad) Dosimetry Ionization Chamber, provided and calibrated by GSF staff (W. Panzer, GSF) Dose rate: ≈ 20 krad(SiO2)/h Integrated Spectrum with known absorption coeff. of SiO2 (A. Pahlke, HLL) Dose rate: ≈9 krad(SiO2)/h July, 2005 Ladislav Andricek, MPI für Physik, HLL

Basic Characteristics - pre and post-irradiation VG=-6V VG=-10V ID (μA) ID (μA) VG=-9V VG=-4V VG=-8V VG=-2V VG=-7V -VD (V) -VD (V) July, 2005 Ladislav Andricek, MPI für Physik, HLL

Subtreshold slope  interface traps s=85mV/dec s=155mV/dec Vth=-0.2V Vth=-4.5V Literature: after irradiation (1Mrad) of 200 nm oxide: Nit ≈ 1013 cm-2 300 krad : Nit≈2·1011 cm-2 1 Mrad : Nit≈7·1011 cm-2 July, 2005 Ladislav Andricek, MPI für Physik, HLL

Clear Efficiency Study mini matrix devices in laser setup 9/10/2018 Clear Efficiency Study mini matrix devices in laser setup 1x CLEAR then sample 500x in 2.5ms (CLEAR + SAMPLE) 500x  complete clear: noise minimal Region of "complete clear" FWHM of noise peak Clear Amplitude (V) clear duration = 100ns July, 2005 Ladislav Andricek, MPI für Physik, HLL Ladislav Andricek, MPI Munich

Complete clear achieved with static clear gate ! 9/10/2018 Clear Efficiency Study mini matrix devices in laser setup Scan wide parameter space of Clear Gate and Clear Voltage Study various designs, geometries (length of clear gate) and operating conditions (static or clocked clear gate) Region of "complete clear" Clear Gate Voltage (V) Static Clear Voltage (V), Clear off = 2V Complete clear achieved with static clear gate ! Required voltages are small (5-7V) – very important for future SWITCHER! July, 2005 Ladislav Andricek, MPI für Physik, HLL Ladislav Andricek, MPI Munich

Fast Clearing Complete clear in only 10-20 ns @ DVclear = 11-7 V 9/10/2018 Fast Clearing Study clear efficiency for short clear pulses Device with common clear gate UClear-off = 3 V Complete clear in only 10-20 ns @ DVclear = 11-7 V July, 2005 Ladislav Andricek, MPI für Physik, HLL Ladislav Andricek, MPI Munich

The Vertex Detector at the ILC 9/10/2018 The Vertex Detector at the ILC pixel size: 20-30 µm low mass: 0.1 %Xo per layer close to IP, r = 15 mm (1st layer) 20 ns/row read out time 5 barrels – stand alone tracking TESLA TDR Design 1st layer module: 100x13 mm2, 2nd-5th layer : 125x22 mm2  ∑120 modules July, 2005 Ladislav Andricek, MPI für Physik, HLL Ladislav Andricek, MPI Munich

The Vertex Detector at the ILC 9/10/2018 The Vertex Detector at the ILC ‘Holes’ in frame can save material Chips are thinned to 50 µm, connection via bump bonding Thinned sensor (50 µm) in active area Thick support frame (~300 µm) r=15.5 mm 8 Modules in Layer1 Cross section of a module July, 2005 Ladislav Andricek, MPI für Physik, HLL Ladislav Andricek, MPI Munich

July, 2005 Ladislav Andricek, MPI für Physik, HLL

Background  Speed Requirements 9/10/2018 Background  Speed Requirements 337 ns Large occupancy in Layer 1 with integration of the entire bunchtrain!!!  read 10 to 20 times per train ~ 50µs readout time per module, 5000 rows in layer 1, read out on both sides Required clock rate: 25 to 50 MHz @ Layer I ( up to 20 ns/row) background: mainly e+/e- pair production due to beamstrahlung [C.Büssser, DESY] July, 2005 Ladislav Andricek, MPI für Physik, HLL Ladislav Andricek, MPI Munich

Matrix operation Readout sequence 9/10/2018 Matrix operation TROW Readout sequence Select one row via external Gates and measure Pedestal + Signal current Reset that row and measure pedestal currents Collected charge in internal gate ~ (Difference of both currents) continue with next row ... Only selected rows dissipate power but Sensor still sensitive even with the DEPFET in OFF state July, 2005 Ladislav Andricek, MPI für Physik, HLL Ladislav Andricek, MPI Munich

Switcher ASIC (Multiplexer) 9/10/2018 Switcher ASIC (Multiplexer) 4.6 mm 4.8 mm 64 channels with 2 analog MUX outputs Can switch up to 25 V digital control ground + supply floating fast internal sequencer for programmable pattern (operates up to 80MHz) Daisy chaining of several chips on a module possible 0.8µm AMS HV technology Radiation tolerance may be problematic! 20V ! 2x64 outputs with spare pads Pads for daisy chain control inputs Switching 20V @ 30MHz July, 2005 Ladislav Andricek, MPI für Physik, HLL Ladislav Andricek, MPI Munich

CURO ASIC (Drain Readout) 9/10/2018 CURO ASIC (Drain Readout) Digital part: works up to 110 MHz Noise (CURO) as calculated: about 40nA expected signal (MIP) in thin DEPFET 50 µm * 80 e-/µm * gq (0.4nA/e-) = 1.6 µA  S/N ≈ 40 Analog Part works with 50MHz (means 100MHz sampling ! ) Digital Part (Hit Finder): works up to 110MHz Power consumption: 2.8 mW / channel @ 50MHz July, 2005 Ladislav Andricek, MPI für Physik, HLL Ladislav Andricek, MPI Munich

DEPFET prototype system 9/10/2018 DEPFET prototype system … the operation of a matrix is illustrated. The drain currents of the pixels are read out in parallel by a new readout chip named CURO, while the matrix is switched and cleared row wise. the pedestal subtraction is done directly on the chip, so that the readout procedure is as follows: Select one row via external Gates and measure Pedestal + Signal current Reset that row and measure pedestal currents Collected charge in internal gate is then directly proportional to the difference of both currents continue with next row ... Since only one row is active at a time and the rest is switched off, the power consumption of this matrix is minimized and does NOT depend on the no. of rows. That operation mode is very fast, but it requires that the pedestal current of each pixel is stable. I will come to this point later… On the right you see a photo of a DEPFET based system for a biomedical application, which was assembled in Bonn. On the next slide no 6 …. July, 2005 Ladislav Andricek, MPI für Physik, HLL Ladislav Andricek, MPI Munich

ILC DEPFET-System in the Lab 9/10/2018 ILC DEPFET-System in the Lab irradiation with 55Fe (6keV g, 1700 e-) 2.7 mm 3.4 mm 10µm thick Tungsten-Mask ILC system performance in the lab: High speed: row rate 0.6 MHz Noise: 230 e- Noise contributions: ~ 100e- from CURO etc. ~ 60e- from I2U converter (CURO → ADC) ~ noise pickup of I2U converter 1keV…13keV 13keV…1MeV July, 2005 Ladislav Andricek, MPI für Physik, HLL Ladislav Andricek, MPI Munich

Test Beam Setup (Jan / Feb 2005 @ T24, DESY) 9/10/2018 Test Beam Setup (Jan / Feb 2005 @ T24, DESY) Beam T24 @ DESY, Jan/Feb. 2005 Electrons @ 4GeV Reference telescope: 4 Si-strip planes (pitch in x- and y: 50µm) Two matrices have been tested with 4 x 128 pixels of 36µm x 28.5µm 3 x 3 mm2 Scintillator DEPFET System Telescope- Modules Scintillator July, 2005 Ladislav Andricek, MPI für Physik, HLL Ladislav Andricek, MPI Munich

Test Beam Results: Online Correlations Beam spot on (small) DEPFET Beam spot on telescope correlation telescope x  DEPFET x Event rate: 10Hz collected 10 million events highE / non-highE in beam data analysis ongoing July, 2005 Ladislav Andricek, MPI für Physik, HLL

Test beam: Event Displays single hit cluster Some d-electrons with perpendicular tracks ! (range of tracks is ~ consistent with measured energy of few 100keV) Cluster: Only 1-2 pixels hit in x and y at perpendicular beam incidence Much more information about event structure due to spectroscopic quality of the device! July, 2005 Ladislav Andricek, MPI für Physik, HLL

Module Concept/Power Consumption 9/10/2018 Module Concept/Power Consumption Total power consumption of the vtx-d in the active region (TDR design, 25 mm pixel) DEPFET matrix only: 1st layer : 2 rows active, 30 μA ∙ 5V ∙ 650 ∙ 2 ∙ 8 = 1.6 W 2nd .. 5th layer: 1 row active, 30 μA ∙ 5V ∙ 1100 ∙ 1 ∙ 112 = 18.5 W Steering chips: assuming 0.15 mW for an inactive, 300 mW for an active channel 1st layer : [(4998 ∙ 0.15 mW)+(2 ∙ 300mW)] ∙ 8 = 10.8 W 2nd ..5th layer: [(6249 ∙ 0.15 mW)+(1 ∙ 300mW)] ∙ 112 = 138.6 W Σ active region ≈ 170 W % duty cycle ILC 1/200  ≈ 0.9 W sketch of a 1st layer module r/o chips (current version):2.8 mW/chn. for the whole vtx-d: ≈ 2W July, 2005 Ladislav Andricek, MPI für Physik, HLL Ladislav Andricek, MPI Munich

A short intermediate summary... 1. Charge generation and first amplification in a fully depleted pixel cell:  good Signal/Noise 2. No charge transfer needed:  fast read out  better rad. hardness against hadronic irradiation 3. Wafer scale arrays possible, no stitching of reticles (chips) needed:  easier module construction, less material 4. Only one row at a time active, read out at the ladder end:  low power consumption, less material for cooling How to build and handle thin (tens of μm) DEPFET arrays?? July, 2005 Ladislav Andricek, MPI für Physik, HLL

Processing thin detectors 9/10/2018 Processing thin detectors Top Wafer Handle <100> Wafer a) oxidation and back side implant of top wafer b) wafer bonding and grinding/polishing of top wafer c) process  passivation open backside passivation d) anisotropic deep etching opens "windows" in handle wafer July, 2005 Ladislav Andricek, MPI für Physik, HLL Ladislav Andricek, MPI Munich

Processing thin detectors 9/10/2018 Processing thin detectors Top Wafer Handle <100> Wafer a) oxidation and back side implant of top wafer b) wafer bonding and grinding/polishing of top wafer c) process  passivation open backside passivation d) anisotropic deep etching opens "windows" in handle wafer 50 μm, 4 diodes, 10 mm2 reverse current (pA) 700..850 pA/cm2 Al July, 2005 Ladislav Andricek, MPI für Physik, HLL Ladislav Andricek, MPI Munich

PiN Diodes on thin Silicon -Type II 9/10/2018 PiN Diodes on thin Silicon -Type II Al SiO2 p+ unstructured n+ on top structured p+ in bond region 0.09 cm2 .. 6.5 cm2 diodes Type II: Implants like DEPFET config. Diodes of various sizes: 0.09 cm2 – 6.5 cm2 surface generated edge current included reverse currents at 5 V bias ~900 pA/cm2 reverse current (nA) area (cm2) contact opening and metallization after etching of the handle wafer July, 2005 Ladislav Andricek, MPI für Physik, HLL Ladislav Andricek, MPI Munich

Estimated Material Budget (1st layer): 9/10/2018 Material Budget Estimated Material Budget (1st layer): Pixel area: 100x13 mm2, 50 μm : 0.05% X0 steer. chips: 100x2 mm2, 50 μm : 0.008% X0 (massive) Frame :100x4 mm2, 300 μm : 0.09% X0 perforated frame: 0.05 % X0 total: 0.11 % X0 reduce frame material!!!  "support grid" July, 2005 Ladislav Andricek, MPI für Physik, HLL Ladislav Andricek, MPI Munich

Conclusion but it's only the beginning of a long game .... 9/10/2018 Conclusion Achievements: Present Pixel size: 24x33 µm2 – can go to ~ 20x20 µm2, limited only by manufacturing equipment Complete clearing works with short (10ns) clear pulses at moderate voltages. No need to clock clear gate Radiation tolerance (threshold voltage shift) demonstrated up to 1Mrad Technology for thin (≤ 50µm) detectors established (total budget of sensor 0.11% X0) Advantages DEPFET Charge collection in fully depleted bulk with high charge collection field High S/N (~40 at 100e noise), high spatial resolution (expect ~2µm) Low average power dissipation for full ILC system (4W) Fast readout possible (some 10 MHz) Low material We don't see any "show stoppers" for the integration of an ILC vertex detector based in DEPFETs. but it's only the beginning of a long game .... July, 2005 Ladislav Andricek, MPI für Physik, HLL Ladislav Andricek, MPI Munich

The long (and incomplete) list of open items 1:- DEPFET specific conceptual design of the vertex detector #layers?, pixel size?, impact of the inhomogenously distributed material on the physics results..... 2:- Analyse quantitatively the mechanical and thermal properties of the ladders FEA and measurements 3:- Development of the interconnect and assembly technology for the modules bump bonding, wedge bonding with the thin modules? 4:- Irradiation and characterization of matrices, chips and the entire system with gammas, hadrons, electrons... 5:- EMI: Is it really a problem?? 6: - ...... Next steps within the collaboration: Operate complete system at full ILC speed  Bonn, MPI Beam Tests at CERN (pos. resolution??)  all Produce thin sensors with larger matrices  MPI Design new SWITCHER  Mannheim Design new CURO (deeper FIFO, standby mode, ADC?,)  Bonn July, 2005 Ladislav Andricek, MPI für Physik, HLL

Project Status - in Summary steering chips Switcher II thinning technology Technology development r/o chips Curo II tolerance against ion. radition system in the lab and in the beam July, 2005 Ladislav Andricek, MPI für Physik, HLL

Mechanical Dummies - how thin can we get?? - window dimensions: 9/10/2018 Mechanical Dummies - how thin can we get?? - window dimensions: (50x13)/4 mm2 6.5x6.5 mm2 80x10.4 mm2 (80% of a tesla sensor) (50x13)/2 mm2 50x13 mm2 10 "SOI" wafers with various top layer thicknesses 24 - 29 micron (3 Wafers) 36 - 38 micron (3 Wafers) 43 - 51 micron (4 Wafers) 26 μm 51 μm July, 2005 Ladislav Andricek, MPI für Physik, HLL Ladislav Andricek, MPI Munich

Mechanical Dummies the mirror image of a 5mm grid… 9/10/2018 Mechanical Dummies the mirror image of a 5mm grid… polished back side of a 40 μm thin top wafer after deep etching with TMAH July, 2005 Ladislav Andricek, MPI für Physik, HLL Ladislav Andricek, MPI Munich

Mechanical Dummies the mirror image of a 5mm grid… 9/10/2018 Mechanical Dummies the mirror image of a 5mm grid… 40 μm top wafer side: patterned aluminum layer (ATLAS strip detector prototype mask) July, 2005 Ladislav Andricek, MPI für Physik, HLL Ladislav Andricek, MPI Munich

Mechanical Dummies the mirror image of a 5mm grid… 9/10/2018 Mechanical Dummies the mirror image of a 5mm grid… focus on the mirror image: no distortions visible, even after single sided metallization!! July, 2005 Ladislav Andricek, MPI für Physik, HLL Ladislav Andricek, MPI Munich