RISC-V Tejas: A RISC-V Port of the Tejas Architectural Simulator Dr. Smruti R. Sarangi Department of Computer Science and Engineering Indian Institute of Technology Delhi

The RISC-V ISA Most popular open ISA Initially purely academic, now enjoying industry interest

The RISC-V ISA Most popular open ISA Governed by the RISC-V Foundation Companies supporting the foundation include Google, Microsoft, IBM, HP, NXP, NVIDIA, Qualcomm, Micron, Huawei, AMD

The RISC-V ISA Most popular open ISA Governed by the RISC-V Foundation Expected to increase the quality of both software and hardware Open standards increase competition

The RISC-V ISA Most popular open ISA Governed by the RISC-V Foundation Expected to increase the quality of both software and hardware Expected initial thrust is in the embedded domain Being a RISC ISA, cores can be simpler, thereby consuming low power

The RISC-V ISA NVIDIA has begun developing RISC-V based cores The Shakti group at IIT Madras is developing 7 classes of RISC-V based cores Low power embedded version High performance server class version Fault Tolerant version

Design a Processor Simulate

RISC-V Tejas

Steps to Realize RISC-V Tejas (1) Emulating RISC-V applications

Emulating RISC-V Applications X86 App App Intel Pin OS x86 applications Qemu Full system simulation Kernel Java App GPU Ocelot Jikes RVM GPU workloads Java applications RISC-V App RISC-V App OS (Linux/FreeBSD) Spike RISCVEMU Application only mode Full System Simulation mode

Steps to Realize RISC-V Tejas (1) Emulating RISC-V applications (2) Translating to VISA

Translating RISC-V to VISA Elegant correspondence between RISC-V and VISA VISA is also a RISC ISA RISC-V VISA Instruction formats: Register-register, register-immediate, register-register-immediate, immediate Register-register, register-immediate, immediate Computational instructions: ADD, SUB, SLT, SLL, SRL, SRA, AND, OR, XOR, LUI, AUIPC, NOP INTEGERALU, MOV, NOP (complete coverage in terms of modeling compute latencies, and inter-instruction dependencies) Control transfer instructions: JAL, JALR, BEQ, BNE, BLT, BGE JUMP, BRANCH (complete coverage) Memory instructions: LOAD, STORE (load-store architecture) LOAD, STORE (also a load-store architecture) Memory model: FENCE

(RISC-V to VISA translation) X86 instruction Spike (RISC-V to VISA translation) Input Application (RISC-V) load %x1, %x2, #16, %x3 Translator Input Application: X86 Simulation Engine: VISA Spike VISA instruction (static) VISA static load <%reg1, ?>, %reg2, %reg3 Runtime information Fuse Packet <IP,value,target> (0x10, memread, 0x1234) VISA instruction (dynamic) VISA dynamic load <%reg1, 0x1234 >, %reg2, %reg3

Guest OS VMM Guest H/W Guest H/W RISCVEMU RISCVEMU Native OS Native OS RISCVEMU (Full System Mode) App1 App2 App1 App2 Guest OS1 Guest OS2 Guest OS VMM Guest H/W Guest H/W RISCVEMU RISCVEMU Native OS Native OS Native H/W Native H/W Important for studying the execution of different workloads in native as well as virtualized environments

Guest OS Guest H/W RISCVEMU RISCVEMU Emulation (Full System Mode) Translation App1 App2 Guest OS Guest H/W RISCVEMU ip, assembly, load %x1, %x2, #16, %x3 ip, memread, addr X Mapping Available ? Yes load <%reg1, X>, %reg2, %reg3 Translate And cache No Fuse

Guest OS Guest H/W RISCVEMU RISCVEMU (Framework) Traces contain: Regular (memory, and branch) Assembly text of each instruction OS Events System call ID Interrupt ID Privilege level switches in x86 Research specific (OS instrumentation) App1 App2 Guest OS Guest H/W RISCVEMU

Steps to Realize RISC-V Tejas (1) Emulating RISC-V applications (2) Translating to VISA The rest remains unchanged!