ESE532: System-on-a-Chip Architecture Day 21: April 5, 2017 VLSI Scaling Penn ESE532 Spring 2017 -- DeHon

Today VLSI Scaling Rules Effects Historical/predicted scaling Variations (cheating) Limits Note: gory equations  goal is to understand trends Give equations … then push through scaling implications together Penn ESE532 Spring 2017 -- DeHon

Message Technology advances rapidly Must account for in understanding …platform will be available …platforms will be inexpensive …what our competitors can build …new challenges and opportunities Penn ESE532 Spring 2017 -- DeHon

Why Care? In this game, we must be able to predict the future Technology advances rapidly Reason about changes and trends Re-evaluate prior solutions given technology at time X. Make direct comparison across technologies E.g. to understand older designs What comes from process vs. architecture Penn ESE532 Spring 2017 -- DeHon

Why Care: Custom SoC Cannot compare against what competitor does today but what they can do at time you can ship Development time > Technology generation Careful not to fall off curve lose out to someone who can stay on curve Penn ESE532 Spring 2017 -- DeHon

Scaling Old Premise: features scale “uniformly” Parameters: everything gets better in a predictable manner Parameters: l (lambda) -- Mead and Conway F -- Half pitch – ITRS (F=2l) S – scale factor – Rabaey F’=S×F Penn ESE532 Spring 2017 -- DeHon

ITRS Roadmap Semiconductor Industry rides this scaling curve Try to predict where industry going (requirements…self fulfilling prophecy) http://public.itrs.net http://www.semiconductors.org/main/2015_international_technology_roadmap_for_semiconductors_itrs/ Penn ESE532 Spring 2017 -- DeHon

Preclass Scale factor S from 28nm  20nm? Penn ESE532 Spring 2017 -- DeHon

MOS Transistor Scaling (1974 to present) [0.5x per 2 nodes] Pitch Gate [from Andrew Kahng] Source: 2001 ITRS - Exec. Summary, ORTC Figure Penn ESE532 Spring 2017 -- DeHon

Half Pitch (= Pitch/2) Definition (Typical MPU/ASIC) DRAM) Poly Pitch Metal [from Andrew Kahng] Source: 2001 ITRS - Exec. Summary, ORTC Figure Penn ESE532 Spring 2017 -- DeHon

Scaling Calculator + Node Cycle Time: 250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16 0.5x 0.7x N N+1 N+2 Node Cycle Time (T yrs): *CARR(T) = [(0.5)^(1/2T yrs)] - 1 CARR(3 yrs) = -10.9% CARR(2 yrs) = -15.9% * CARR(T) = Compound Annual Reduction Rate (@ cycle time period, T) Log Half-Pitch Linear Time 1994 NTRS - .7x/3yrs Actual - .7x/2yrs Scaling Calculator + Node Cycle Time: [from Andrew Kahng] Source: 2001 ITRS - Exec. Summary, ORTC Figure Penn ESE532 Spring 2017 -- DeHon

Warning Dive into detail equations Not expect you necessarily know before Unless took 370, 570, 534… Won’t expect you use later …but, you want to have an idea of the implications (area, performance, energy) If I just showed you results I think would be hard to follow Not engaged So, we will do calculations together Penn ESE532 Spring 2017 -- DeHon

Dimensions Channel Length (L) Channel Width (W) Oxide Thickness (Tox) Penn ESE532 Spring 2017 -- DeHon

Scaling Channel Length (L) Channel Width (W) Oxide Thickness (Tox) Doping (Na) Voltage (V) Penn ESE532 Spring 2017 -- DeHon

Full Scaling (Ideal Scaling, Dennard Scaling) Channel Length (L) S Channel Width (W) S Oxide Thickness (Tox) S Doping (Na) 1/S Voltage (V) S Penn ESE532 Spring 2017 -- DeHon

Effects on Physical Properties? Area Capacitance Resistance Threshold (Vth) Current (Id) Gate Delay (tgd) Wire Delay (twire) Energy Power Go through full (ideal) …then come back and ask what still makes sense today These are more the take-aways Penn ESE532 Spring 2017 -- DeHon

S=0.7 Area [0.5x per 2 nodes] F FS Area impact? A = L × W A  AS2 28nm  20nm 50% area 2× capacity same area L W S=0.7 [0.5x per 2 nodes] Pitch Gate Penn ESE532 Spring 2017 -- DeHon

Preclass When will have 100-core processor What feature size? What time frame? Penn ESE532 Spring 2017 -- DeHon

Capacity Scaling from Wikipedia Penn ESE532 Spring 2017 -- DeHon

Capacitance Cox= eSiO2/Tox Tox S×Tox Cox  Cox/S Capacitance per unit area scaling: Cox= eSiO2/Tox Tox S×Tox Cox  Cox/S Penn ESE532 Spring 2017 -- DeHon

Capacitance Cgate= A×Cox A  A×S2 Cox  Cox/S Cgate  S×Cgate Gate Capacitance scaling? Cgate= A×Cox A  A×S2 Cox  Cox/S Cgate  S×Cgate Penn ESE532 Spring 2017 -- DeHon

Resistance Resistance scaling? R=rL/(W*t) W S×W L, t similar R  R/S Penn ESE532 Spring 2017 -- DeHon

Threshold Voltage VTH S×VTH Penn ESE532 Spring 2017 -- DeHon

Current Id=(mCOX/2)(W/L)(Vgs-VTH)2 Vgs=V S×V VTH S×VTH W S×W L S×L Saturation Current scaling? Id=(mCOX/2)(W/L)(Vgs-VTH)2 Vgs=V S×V VTH S×VTH W S×W L S×L Cox  Cox/S Id S×Id Penn ESE532 Spring 2017 -- DeHon

Gate Delay Gate Delay scaling? tgd=Q/I=(CV)/I V S×V Id  S×Id C  S×C tgd  S×tgd Penn ESE532 Spring 2017 -- DeHon

Overall Scaling Results, Transistor Speed and Leakage Overall Scaling Results, Transistor Speed and Leakage. Preliminary Data from 2005 ITRS. Intrinsic Transistor Delay, t = CV/I (lower delay = higher speed) Leakage Current (HP: standby power dissipation issues) HP Target: 17%/yr, historical rate LOP LSTP LSTP Target: Isd,leak ~ 10 pA/um HP HP = High-Performance Logic LOP = Low Operating Power Logic LSTP = Low Standby Power Logic 17%/yr rate Planar Bulk MOSFETs Advanced MOSFETs Penn ESE532 Spring 2017 -- DeHon

Wire Delay Wire delay scaling? twire=RC R  R/S C  S×C twire  twire …assuming (logical) wire lengths remain constant... Penn ESE532 Spring 2017 -- DeHon

Impact of Wire and Gate Delay Scaling If gate delay scales down but wire delay does not scale, what does that suggest about the relative contribution of gate and wire delays to overall delay as we scale? Penn ESE532 Spring 2017 -- DeHon

Energy V S×V C  S×C E  S3×E Switching Energy per operation scaling? E=1/2 CV2 V S×V C  S×C E  S3×E Penn ESE532 Spring 2017 -- DeHon

Power Dissipation (Dynamic) Capacitive (Dis)charging scaling? P=(1/2)CV2f V S×V C  S×C P S3×P Increase Frequency? tgd  S×tgd So: f  f/S ? P  S2×P Penn ESE532 Spring 2017 -- DeHon

Effects? Area S2 Capacitance S Resistance 1/S Threshold (Vth) S Current (Id) S Gate Delay (tgd) S Wire Delay (twire) 1 Energy S3 Power S2S3 Penn ESE532 Spring 2017 -- DeHon

Power Density P S2P (increase frequency) P S3P (dynamic, same freq.) A  S2A Power Density: P/A two cases? P/A  P/A increase freq. P/A  S×P/A same freq. Penn ESE532 Spring 2017 -- DeHon

Power Density P/A  P/A very important Says, it doesn’t get any harder to cool as we scale exponentially to More gates switching Higher clock rates Don’t create an cooling bottleneck Penn ESE532 Spring 2017 -- DeHon

Cheating… Don’t like some of the implications High resistance wires Higher capacitance Atomic-scale dimensions …. Quantum tunneling Not scale speed fast enough Penn ESE532 Spring 2017 -- DeHon

Improving Resistance R=rL/(W×t) W S×W L, t similar R  R/S What might we do? Don’t scale t quite as fast  now taller than wide. Decrease r (copper) – introduced 1997 http://www.ibm.com/ibm100/us/en/icons/copperchip/ Penn ESE532 Spring 2017 -- DeHon

Penn ESE532 Spring 2017 -- DeHon

3D View Source: https://en.wikipedia.org/wiki/File:Silicon_chip_3d.PNG Penn ESE532 Spring 2017 -- DeHon

Capacitance and Leakage Capacitance per unit area Cox= eSiO2/Tox Tox S×Tox Cox  Cox/S What’s wrong with Tox = 1.2nm? source: Borkar/Micro 2004 Penn ESE532 Spring 2017 -- DeHon

Capacitance and Leakage Capacitance per unit area Cox= eSiO2/Tox Tox S×Tox Cox  Cox/S What might we do? Reduce Dielectric Constant e (interconnect) and Increase Dielectric to substitute for scaling Tox (gate quantum tunneling) Penn ESE532 Spring 2017 -- DeHon

High-K dielectric Survey Wong/IBM J. of R&D, V46N2/3P133—168, 2002 Penn ESE532 Spring 2017 -- DeHon

Improving Gate Delay Normal scale tgd=Q/I=(CV)/I V S×V Id  S×Id Id=(mCOX/2)(W/L)(Vgs-VTH)2 Id  S×Id C  S×C tgd  S×tgd What happens if don’t scale V? (note V impacts I) Don’t scale V: VV II/S tgd  S2×tgd Penn ESE532 Spring 2017 -- DeHon

…But Power Dissipation (Dynamic) Capacitive (Dis)charging P=(1/2)CV2f V V C  S×C Increase Frequency? f  f/S2 ? P  P/S If not scale V, power dissipation not scale down. Penn ESE532 Spring 2017 -- DeHon

…And Power Density P P/S (increase frequency) But… A  S2×A What happens to power density? P/A  (1/S3)P/A Power Density Increases …this is where some companies have gotten into trouble… Penn ESE532 Spring 2017 -- DeHon

Historical Voltage Scaling http://software.intel.com/en-us/articles/gigascale-integration-challenges-and-opportunities/ …and, we’re running into limits prevent voltage scaling going forward. Penn ESE532 Spring 2017 -- DeHon

uP Power Density Watts The Future of Computing Performance: Game Over or Next Level? National Academy Press, 2011 Penn ESE532 Spring 2017 -- DeHon http://www.nap.edu/catalog.php?record_id=12980

Power Density Has become the new bottleneck Can put more transistors on a chip than we can afford to turn on Can afford to operate at the frequency at which they are capable of switching Energy and Power, not capacity, limits performance Penn ESE532 Spring 2017 -- DeHon

uProc Clock Frequency MHz The Future of Computing Performance: Game Over or Next Level? National Academy Press, 2011 Penn ESE532 Spring 2017 -- DeHon http://www.nap.edu/catalog.php?record_id=12980

Penn ESE532 Spring 2017 -- DeHon

Physical Limits Doping? Features? Penn ESE532 Spring 2017 -- DeHon

Physical Limits Depended on Eventually bulk effects doping current (many electrons) mean free path in conductor localized to conductors Eventually single electrons, atoms distances close enough to allow tunneling Penn ESE532 Spring 2017 -- DeHon

Dopants/Transistor Penn ESE532 Spring 2017 -- DeHon 10 100 1000 10000 500 250 130 65 32 16 Technology Node (nm) Mean Number of Dopant Atoms Starting at the beginning… As our devices scale to the atomic scale, we must deal with the fact that the low level physics of the placement and behavior of atoms and electrons is statistical in nature. Note on graphs: The left graphs shows how the number of dopants decreases as we scale to smaller technology nodes. Around the 65nm node, we are already down to roughly 100 dopants per device. Since dopants are placed statistically, we always see a range of actual dopants. As the total number of dopants (N) decreases, the variance among devices increases. Very roughly, the variance in the number of dopants in a device goes as N-0.5 (i.e. 1/sqrt(N) ). So, at 100 dopants, we have a variance of 10%. The graph on the right plots this variance. The effective variance is actually larger than this because, at these small numbers, actual placement of the dopants matters as well as the number. This underscores the fact that increased variance is arising directly from these small number effects. Penn ESE532 Spring 2017 -- DeHon

Leads to Variation [Borkar, IEEE Micro Nov.-Dec. 2005] Penn ESE532 Spring 2017 -- DeHon

Conventional Scaling Ends in your lifetime Perhaps already has: "Basically, this is the end of scaling.” May 2005, Bernard Meyerson, V.P. and chief technologist for IBM's systems and technology group Penn ESE532 Spring 2017 -- DeHon

Bob Colwell March 2013 Penn ESE532 Spring 2017 -- DeHon

Feature Size Scaling ITRS IEEE Spectrum, Sep. 2016 Penn ESE532 Spring 2017 -- DeHon

Intel says they’ve got 10nm covered Penn ESE532 Spring 2017 -- DeHon

Conventional Scaling Ends in your lifetime Perhaps already: "Basically, this is the end of scaling.” May 2005, Bernard Meyerson, V.P. and chief technologist for IBM's systems and technology group Dennard Scaling ended Feature scaling end at 10nm? Transistor count integration may continue… E.g. 3D Penn ESE532 Spring 2017 -- DeHon

Finishing Up... Penn ESE532 Spring 2017 -- DeHon

Big Ideas [MSB Ideas] Moderately predictable VLSI Scaling unprecedented capacities/capability growth for engineered systems change be prepared to exploit account for in comparing across time …but not for much longer Penn ESE532 Spring 2017 -- DeHon

Big Ideas [MSB-1 Ideas] Uniform scaling reasonably accurate for past couple of decades Area increase 1/S2 Real capacity maybe a little less? Gate delay decreases (S) …maybe a little less Wire delay not decrease, maybe increase Overall delay decrease less than (S) Lack of V scale  Power density limit Penn ESE532 Spring 2017 -- DeHon

Admin Project 4x and area Milestone Due Friday Penn ESE532 Spring 2017 -- DeHon