Placement study at ESA Filomena Decuzzi David Merodio Codinachs TEC-EDM

Outline PURPLE platform VPR: External Placement Engine VPR CAD Flow Architectural differences Congestion factor Preliminary results 2

Atmel FPGA 3rd User Group Workshop PURPLE Placement engine Placement engine Front-end Back-end Netlist description Logic position design.fgd design_replace.fgd Atmel FPGA 3rd User Group Workshop Oct 07, 2010 3

VPR: general architecture From VPR website (and several papers): “VPR was written to allow circuits to be placed and routed on a wide variety of FPGAs to facilitate comparisons of different architectures.” “It takes two input files, a netlist describing the circuit to be placed and routed, and a description of the FPGA architecture.” Feasible to use it also for Atmel architecture 4

Versatile Place Route FPGA placement and routing tool Copyright University of Toronto Timing-driven placement VPR paper of 1997 ranks 4th in the most cited FPGA papers in google scholar Optimization engine based on simulated annealing http://www.eecg.toronto.edu/~vaughn/vpr/vpr.html

VPR CAD Flow Input Output Logic blocks in two-level hierarchy: Benchmark Architecture description Output Placement description Routing description Timing analysis Logic blocks in two-level hierarchy: Basic Logic Element (BLE): 1 LUT+1 FF Cluster (n BLEs)

T-VPack T-Vpack perform a timing-driven packing in clusters Fully connected cluster: sharing of all the input and output between all the BLE of the cluster (intra-cluster routing) Logic Cluster Not supported by Atmel architecture

VPR: general enough? Recall (from VPR website and several papers): “VPR was written to allow circuits to be placed and routed on a wide variety of FPGAs to facilitate comparisons of different architectures.” “It takes two input files, a netlist describing the circuit to be placed and routed, and a description of the FPGA architecture.” After deeper study: Several architectural differences complicates the adaptation of VPR to support Atmel architecture See next slides 8

Routing architecture (1) VPR routing architecture Atmel routing architecture

Routing architecture (2) VPR switch box Atmel direct connection

Architecture gap Intra-cluster routing Inter-cluster routing Absence of fully-connected cluster in Atmel architecture Inter-cluster routing Absence of switch box in Atmel architecture Direct connection Partially supported by VPR VPR “as is” produces a very dense placement non routable 11

VPR Cost Timing cost Wiring cost previous timing cost number of nets in the circuit previous wiring cost compensation factor constant [0,1] horizontal span weight critical connection [1,max(default 8)] vertical span

VPR_congestion Yue Zhuo, Hao Li and Saraju P. Mohanty “A congestion driven placement algorithm for fpga synthesis”,In proceeding of the International Conference on Field Programmable Logic and Application,2006 number of bouding boxes covering horizontal size chip vertical size chip small positive integer Always When close to 1 the placement is balanced When greater than 1 the placement is congested ≥ 1

Ex1 Figaro solution 2714 104 2409 2276 133 979 10111 6005 4106 Net IO instance Core Cell netlist instance for routing Macros with RAM Register Buses Local Express

VPR solution VPR VPR_congestion final 714 route contention

VPR_congestion best sol % respect Figaro Net IO instance Core Cell netlist instance for routing Macros with RAM Register Buses Local Express 2714 104 2906 2276 630 979 13051 7110 5941 - 20% 29% 18% 11% final 119 route contention

Conclusion VPR usage is not as generic as initially estimated adaptation to Atmel architecture not trivial VPR ongoing work: Optimization of use of direct connection required Re-define congestion factor on Atmel architecture PURPLE is finished and enables the use of any Placement and Routing Engines Close collaboration with Atmel to keep compatibility with future versions 17