FPGA Configuration Chris Stinson, 1998

Configuration Pins and Dual Purpose I/O Configuration Modes Data Stream Format Configuration Pins and Dual Purpose I/O FPGA Configuration Sequence and Flow Start-up Sequence Daisy Chain Spartan FPGA Config - 4-98

FPGA Configuration Objective: To be able to successfully take a BITstream and configure an FPGA. Debugging techniques General flow of configuration How to debug a board Different methods of configuration

Configuration Modes (4K E/EX/XL/XV) Master Serial Slave Serial Master Parallel Up/Down Peripheral Synchronous Peripheral Asynchronous Express

Configuration Modes Master Serial - FPGA drives configuration clock (CCLK) - Configuration data loaded 1 bit per CCLK Slave Serial - CCLK drive externally from FPGA Master Parallel - FPGA drives address bus - Configuration data loaded 1byte per address - FPGA serializes data, 8 CCLK’s per byte

Configuration Modes Asynchronous Peripheral - Configuration data loaded 1 byte per ‘strobe’ - Ready/Busy Handshaking Synchronous Peripheral - ‘Slave Parallel’ - Configuration data loaded 1 byte per 8 CCLK’s Express - Configuration data loaded 1 byte per CCLK

Additional Address Lines Allows additional addressing for additional space required for daisy-chained devices Used with Master Parallel Mode BITGEN option for EX devices - Option to activate: bitgen -g AddressLines:22 - A18-A21 pulled high by internal pullups Always active in XL/XV devices

Data Stream Format

Configuration Pins CCLK - Bi-Directional Configuration Clock DIN INIT - Master Modes: can be set to fast or slow DIN - Serial input for Configuration Data - Programmable I/O INIT - Error and Power Stabilization Flag

Configuration Pins Program Done - Active low input initiates Configuration Done - Bi-Directional Open-Drain Output indicates completion of Configuration DOUT - Data output for daisy chain - Programmable I/O

Configuration Pins Address Lines (A21 - A0) - Address Bus used in Master Parallel Mode - Programmable I/O Data Lines (D7 - D0) - Data bus used in Master Parallel, Asynchronous/Synchronous Peripheral mode

Configuration Pins Mode Pins (M0, M1, M2) RDY/BSY, CS0, CS1, WS, RS - Mode pins select Configuration Mode - Programmable I/O - must be paced on schematic or instantiated in code - M0: Input, M1: Output, M2: Input - Have weak pullups RDY/BSY, CS0, CS1, WS, RS - Handshaking, chip selects, write and read strobes for Peripheral Modes

Configuration Sequence Power Stabilization Test for Timeout Clear Configuration Memory Test INIT Sample Mode Lines Load Configuration Data CCLK count == Length Count Start-up Sequence

Delaying Configuration Program - Hold PROGAM low - FPGA keeps clearing configuration memory INIT - Use open-collector or open-drain to hold low - Causes FPGA to wait after clearing configuration memory before sampling mode pins

Start-up Sequencing Begins when CCLK equal Length count DONE goes high I/O’s become active GSR asserted

Daisy Chaining FPGA’s Header passed through to all FPGA’s Connect DOUT to DIN of next Tie PROGRAM, DONE, INIT and CCLK together DOUT of first device will remain high until configuration memory full, then passes on extra data to next device

Spartan Only two configuration modes - Master Serial Only one Mode Pin - Slave Serial Only one Mode Pin - Not used as programmable I/O

Software Flow Bitgen Promgen Input is NCD from PAR Output: BIT: binary RBT: ASCII Binary Promgen BIT --> PROM .hex: ASCII hex .mcs, .exo, .tek

Downloading Xchecker Cable Slave Serial FPGA Configuration Readback Verify Readback Capture (up to 4013E) Parallel Cable III (DLC5) FPGA Slave Serial in M1.4 JTAG Configuration in M1.5 CPLD JTAG Programming

Trips and Traps Monotonic Power Stabilization Vcc must rise contiguously Meet rise-time specs (~24ms) Board Noise Clock Glitching Ground Bounce Configuration Software Options Startup Sequence

Trips and Traps What Configuration Mode? Does INIT drive permanently LOW? Does DONE go high? Does LDC go high or HDC go low? Does data enter the device? Does the data on DOUT match expected?

Configuration Lab Purpose: To obtain hands on experience debugging configuration Demo Board: XC4003EPC84 and XC1765 Master Serial Mode

Configuration Lab Determine what is wrong Check mode pins Check CCLK DONE? INIT? LDC/HDC