LHC1 & COOP September 1995 Report G. DARBO / INFN-GENOVA Pixel 1995: some results from WA97 A detector with 500.000 pixels Efficiency Pixel early 1996: LHC1 & COOP LHC1: see M. Campbell & W.Snoeys COOP: Status of the design COOP Architecture Read-out and data encoding LHC1 analog signal control LHC1 precise strobes to individual front-ends Schedule and Plans Availability ATLAS Silicon Tracker Workshop Oxford 18-22 September 1995

LHC1 & COOP September 1995 Report G. DARBO / INFN-GENOVA COOP Highlights COOP Architecture Strobe Delay Logic; Strobe Delay Logic Calibration; Analog Bias Voltage for LHC1; Read-out and data encoding. Schedule and Plans Availability RD 19 Collaboration Meeting CERN 4 September 1995

The New Pixel Detector of WA97

LHC1 / COOP Highlights The LHC1 pixel size is 50x500 m 6 Flip-Flops in each Pixel Cell: T: Test input Flip-Flop DL<2:0>: Delay Adjust register M: Output mask flip-flop D: output data flip-flop Trig. DL0 DL1 DL2 Prea    Coinc D Th RS T M Fast OR Test Input One COOP controls up to 6 LHC1 in a ladder: 16-bit bidirectional data bus 10 analog voltage for LHC1 parameter setting 6 individual strobes (6-bit adj.fer LHC1 LHC1 COOP

The 4 LHC1 Operation Modes: M1 (LHC Mode) DL0 DL1 DL2 Prea    Coinc D Th RS T M Fast OR GATED STROBE 1 2 S1=0 S0=1 CS=0 15 CLK LV1 STR

The 4 LHC1 Operation Modes: M2 & M3 Initialization Mode M2: Load DelayAdjust Flip-Flops Shift IN/OUT the DelayAdjust shift registers. 3x128 clock cycles to load the whole configuration. Destructive readout of loaded values for checking. Asynchronous reset by a RST with S1=1 & S0=0 DL0 DL1 DL2 Prea    Coinc D Th RS T M STROBE FAST OR Mode M3: LoadTest & Mask Flip-Flops Shift IN/OUT the Test and Mask flip-flops. 2x128 clock cycles to load the whole configuration. Destructive readout of loaded values for checking. Asynchronous reset by a RST with S1=1 & S0=1 DL0 DL1 DL2 Prea    Coinc D Th RS T M STROBE FAST OR

LHC1 Chip Pin List 16 Bidirectional Data Lines: 3 Control Lines: D<15:0>: Bidirectional Bus; 3 Control Lines: S<1:0>: Selects the 4 operational modes; RW: Read or Write IN/OUT the LHC1 chip; 3 Timing Lines: STR: Strobe to the front-end; LV1: LV1 trigger; CLK: System Clock; 2 Fast OR Lines: FOE: Fast OR Output Enable; FOO: Fast OR Output; 1 Test Input Line: TST: Test Input Pulse to all the amplifiers selected (T=‘1’); 1 Asynchronous Reset: RST: Reset: S<1;0>=0: Reset all D Flip-Flops; S<1:0>=1: Reset the FastOrDelay shift registers (LHC mode); S<1:0>=2: Reset DL<2:0> registers; S<1:0>=3: Reset M and T flip-flops; 6 Voltage For Parameter Compensation: VTH: Discriminator Threshold; VDL: Coarse Delay Set; VDLA: Fine Delay Adjust; VBIAS: Bias voltage for preamplifier; VCOMP: Compensation for detector leakageVREF: Reference voltage for the previous ones; 8 Power Pins.

COOP Basic Functionality The COOP chip controls up to 6 LHC1 in a ladder The COOP has the basic functions of: Interface between the internal synchronous ladder bus and the external asynchronous bus Supplying 10 bias voltages to the LHC1: 6*VTH: Discriminator Threshold VDL: Coarse Delay Set VDLA: Fine Delay Adjust VBIAS: Bias voltage for preamplifier VCOMP: Compensation for detector leakageProvide fine adjust of strobe delay by ±200 ns with 6-bit resolution. Built in feature of both delay and width calibration for each of the 6 strobe outputs Fast readout, encoding and zero suppresion of pixel hits (a factor 20 speed up in a system configuration is expectedThe COOP basic characteristics are: 110 I/O pins: DIGITAL: 20 Input, 20 Output, 32 Bidirectional; ANALOG: 20 DACs Reference IN, 10 Outputs; POWER: 6+6 Digital (3 V), 3+3 Analog (4.5 V) Chip Size: 45 mm2 (6.926 x 6.523) Number of transistors: 77.025 Technologym, 2 metal CMOS Standard Cells LHC1 LHC1 COOP

COOP Architecture CTRL FIFO DL0 ... DL5 5 CTRL REG V0 V9 9 G. Darbo & P. Musico From/To EXTERNAL CTRL DLY REGS DL0 ... DL5 5 CTRL REG FIFO 256x16 V-REGS V0 ... V9 9 ENC IN-REG OUT-REG MASK-REGS From/To LHC1

COOP Architecture Strobe Delay Logic MASK-REGS 9 ENC FIFO 256x16 5 OUT-REG IN-REG CTRL REG CTRL DLY REGS V-REGS Strobe Delay individually adjusted by 6 x 6-bit registers: ±200 ns total range in 6 ns steps (6 bits) Strobe delay through an inverter chain (256 3-input NOR’s) 4-5 ns STR IN MUX 64 to 1 SEL (6-bits) 6-BITs STR1 STR6 STR IN 5 STR 1 STR 6

COOP Architecture Strobe Delay Logic Calibration Strobe Delay & Width calibration by counting times clock is in coincidence in N events: CNT-UP: clock counter, 16-bit wide CNT-DN: event counter (programmable Measurement selected by 4-bit register (S); S=<1..6>: Strobes from 1 to 6 Width S=<9..14>: Strobes from 1 to 6 Delay MASK-REGS 9 ENC FIFO 256x16 5 OUT-REG IN-REG CTRL REG CTRL DLY REGS V-REGS Strobe width S 5 M U X STR-IN STR 1-6 M U X Strobe delay ZERO S CNT DN CNT UP STOP CLK

COOP Architecture Analog Bias Voltages for LHC1 Calibration Up to 10 voltage outputs8-bit DAC’s plus Voltage buffer are on two sides of COOP peripheryEach DAC plus Buffer use 1 mm of peripheryDAC Voltage reference is 0 V +3 V, Analog supply for buffer is 5 V (nominal, 3 V possibly but out of specification) The 10 Voltages are: 6*VTH: Discriminator Threshold VDL: Coarse Delay Set VDLA: Fine Delay Adjust VBIAS: Bias voltage for preamplifier VCOMP: Compensation for detector leakage The 10 DAC registers are paired into 5 16-bits registers and... chained for reading and writing with the other parameter registers into a circular shift register; 4 clock cycles are needed for pushing in/out a data word; 17 Read / Write operation are needed for full update of parameters 9 ENC FIFO 256x16 5 OUT-REG IN-REG CTRL REG CTRL DLY REGS V-REGS MASK-REGS

COOP to LHC1 Parameter Load & Event R/O Parameters are loaded into the 6 LHC1 by “single word” transfer controlled by VME side: 4 clock cycles for each word intermediate buffering in the COOP complete decoupling between LHC1 and “external world”: all data, control and timing lines are regenerated in the COOP Event is readout and encoded inside the COOP: LHC1 rows are shifted out in sequence: 1 clock cycle per empty row Single column masking for noise pixels: 6 x 16-bit registers are in the parameter registers; row pattern encoded into hit address fifo buffering for 256 hit addresses 9 ENC FIFO 256x16 5 OUT-REG IN-REG CTRL REG CTRL DLY REGS V-REGS MASK-REGS 9 ENC FIFO 256x16 5 OUT-REG IN-REG CTRL REG CTRL DLY REGS V-REGS MASK-REGS

COOP Architecture Summary 17 16-bit Parameter Registers: 5 registers for Strobe Delay; 5 Registers for the 10 DAC’s; 6 Registers for LHC1 columns R /O masking; 1 Register at the R/O encoder input (R/O For test purpose 2 I/O data buffer (in the LHC1 bus interface); Event Readout sequencer: hit address encoder; 256 16-bits fifo: macrocell generated by a silicon compiler; BIST structure for testability; 2.1 x 1.8 mm2 macrocell organized in 64 rows x 64 columns; 23.1 ns cycle time and 13.7 ns access time (worst case industrial); 4.5 mW/port/MHz power consumption. Control logic: 16 bit control register; glue logic and sequencer generated by “Synopsys”: 217 cells used (17 flip-flops) and 10.85 ns longest delay path (worst_IND) (2.16 ns for flip-flop setup time must be added) . 9 ENC FIFO 256x16 5 OUT-REG IN-REG CTRL REG CTRL DLY REGS V-REGS MASK-REGS

LHC1 / COOP System Availability COOP Chip: submitted to silicon foundry the beginning of August first silicon by the end of October; Ceramics: schematic entry ready for layout; 3 layer ceramic will be produced at CERN VME and Interface boards: basic specifications and design started: Conclusions: The whole system ready by the end of the Year; Beam tests next year when beam available