Fabrication Flow VLSI Design UNIT I : Introduction to IC Technology 24/12/2008

Out Line Introduction to VLSI Technology NMOS Fabrication Flow CMOS Fabrication flow Unit Processes

INTRODUCTION The initial stages of the ICs have been essentially bipolar devices. The advent of MOS and subsequently the CMOS technologies have revolutionized the area of Integrated Circuit technology. What have started as small circuits performing simple electronic functions have now become complex chips containing millions of devices performing increasingly complex functions at much lower costs CMOS technologies have been used in the initial stages mostly for digital applications. Now Analog and Mixed signal applications have become very popular

The First Computer

ENIAC - The first electronic computer (1946)

The Transistor Revolution First transistor Bell Labs, 1947

FIRST INTEGRATED CIRCUIT 1958

FIRST ICS 1961

Intel 4004 Micro-Processor 1971 1000 transistors 1 MHz operation

Intel Pentium (IV) microprocessor

INTERNATIONAL SCENARIO & TECHNOLOGY TRENDS DESIGN TECHNOLOGY SINGLE FUNCTION IC TO SYSTEM-ON-CHIP (SOC) ------------------------------------------------------------------------ ASIC on DSM Complex ASIC Plug and Play with a Few IPs System on a Chip µP CORE SRAM ROM µP core SRAM ------ ROM Data Cache ATM ROM Logic I/F MPEG RAM Logic Logic Soft I/F IP Timing-Driven Block-based Platform-Based Design Design Design

INTERNATIONAL SCENARIO & TECHNOLOGY TRENDS PROCESS/FABRICATION TECHNOLOGY MICROELECTRONICS TECHNOLOGY ROAD MAP YEAR --------------------------------------------------------------------------------- 1997 1999 2002 2005 2008 2011 2014 Minimum Feature 250 180 130 100 70 50 35 Size (nm) DRAM capacity 256 Mb 1 Gb 4 G 16 Gb 64Gb 256 Gb IT (introduced) DRAM chip size 280 400 560 790 1120 1580 2240 (mm2) MPU transistors/ 11 M 21 M 40 M 76 M 200 M 520 M 1.4 b (cm2) Frequency (mhz) 375 1200 1600 2000 2500 3000 3674 (across-chip, hi-perf.) Max. wiring levels 6 6-7 7 7-8 8-9 9 10 Power supply 1.8-2.5 1.5-1.8 1.2-1.5 0.9-1.2 0.6-0.9 0.5-0.6 0.37-.42 Voltage Max. wafer 200 300 300 300 450 450 450 Dia (mm) ---------------------------------------------------------------------------------- Source: Semiconductor Industry Association (SIA) 1998 Update Lithography approaching Silicon Lattice (0.5nm) CMOS Speeds Into And Beyond Bipolar Range Move to 12” Wafers in ’00; 18” Wafers in ’09

Moore’s Law In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months

Moore’s Law Electronics, April 19, 1965.

Evolution in Complexity

Transistor Counts 1 Billion Transistors K 1,000,000 100,000 10,000 Pentium® III 10,000 Pentium® II Pentium® Pro 1,000 Pentium® i486 i386 100 80286 10 8086 Source: Intel 1 1975 1980 1985 1990 1995 2000 2005 2010 Projected Courtesy, Intel

Moore’s law in Microprocessors 1000 2X growth in 1.96 years! 100 10 P6 Pentium® proc Transistors (MT) 1 486 386 0.1 286 Transistors on Lead Microprocessors double every 2 years 8086 8085 0.01 8080 8008 4004 0.001 1970 1980 1990 2000 2010 Year Courtesy, Intel

Die size grows by 14% to satisfy Moore’s Law Die Size Growth 100 P6 Pentium ® proc Die size (mm) 486 10 386 286 8080 8086 8085 ~7% growth per year 8008 ~2X growth in 10 years 4004 1 1970 1980 1990 2000 2010 Year Die size grows by 14% to satisfy Moore’s Law Courtesy, Intel

Lead Microprocessors frequency doubles every 2 years 10000 Doubles every 2 years 1000 P6 100 Pentium ® proc Frequency (Mhz) 486 10 386 8085 8086 286 1 8080 8008 4004 0.1 1970 1980 1990 2000 2010 Year Lead Microprocessors frequency doubles every 2 years Courtesy, Intel

Lead Microprocessors power continues to increase Power Dissipation 100 P6 Pentium ® proc 10 486 286 Power (Watts) 8086 386 8085 1 8080 8008 4004 0.1 1971 1974 1978 1985 1992 2000 Year Lead Microprocessors power continues to increase Courtesy, Intel

Power will be a major problem 100000 18KW 5KW 10000 1.5KW 1000 500W Pentium® proc Power (Watts) 100 286 486 8086 10 386 8085 8080 8008 1 4004 0.1 1971 1974 1978 1985 1992 2000 2004 2008 Year Power delivery and dissipation will be prohibitive Courtesy, Intel

Power density too high to keep junctions at low temp 10000 Rocket Nozzle 1000 Nuclear Reactor Power Density (W/cm2) 100 8086 10 Hot Plate 4004 P6 8008 8085 386 Pentium® proc 286 486 8080 1 1970 1980 1990 2000 2010 Year Power density too high to keep junctions at low temp Courtesy, Intel

VLSI TECHNOLOGY This technology makes use of silicon material as the base material. Uses different processes such as Oxidation, Implantation, Diffusion, Deposition etc. ..to form different layers of oxides, nitrides and doped layers. Uses photolithographic techniques for transferring the patterns from mask layers to the wafers. With the above processes selected areas and patterns of doped areas such as wells, source drain diffusions, poly silicon poly gates are defined for forming the device structures. Similarly metal layers are defined for interconnecting these devices into the required circuits

NMOS Transistor Fabrication - process flow (1) Si Substrate (p) SiO2 Field Oxide (Thick Oxide) Oxidation (Layering) Oxide etching (Patterning)

NMOS Transistor Fabrication - process flow (2) Oxidation (Layering) SiO2 Gate Oxide (Thin Oxide) Polysilicon deposition (Layering) Polysilicon etching (Patterning)

NMOS Transistor Fabrication - process flow (3) n type n+ Oxide etching (Patterning) Ion implantation (Doping) Oxidation (Layering) SiO2 Insulated Oxide

NMOS Transistor Fabrication - process flow (4) Oxide etching (Patterning) Metal deposition (Layering) Metal etching (Patterning) Contact windows n+ S D G Si Substrate (p) Al evaporation

CMOS Inverter in N-well Process

CMOS Inverter in N-well Process

UNIT PROCESSES OXIDATION ION IMPLANTATION DIFFUSION LITHOGRAPHY DEPOSITION ETCHING CONTACT PROCESSING METALLIZATION

Wafer Processing Czochralski process Melt silicon at 1425 degrees C molten silicon crystal holder seed direction of pull and rotation Czochralski process Melt silicon at 1425 degrees C Add impurities to dope crystal Spin and gradually extract seed crystal Slice into wafers, 0.25mm to 1.0mm Polish one side, sand-blast the other growing crystal (ingot)

Czochralski Growth k=Cs/Cl 1415 deg C k=Cs/Cl k B: 0.72, Al: 0.0018, Ga: 0.0072, P:0.32, As: 0.27, Sb: 0.02 89

OXIDATION Silicon dioxide is the most important component of VLSI technology Used for gate oxides, isolation oxides, masking, inter-metal dielectrics etc. Thin Oxides Are Used As Gate Oxides Thick oxides are used for isolation and masking Traditionally oxides have been grown through thermal oxidation ( wet and dry) As gate oxides become very thin (< 100 å)the growth process as well as the dielectric strength become critical issues. Deposited oxides or alloys of oxides or high dielectric constant materials become choices.

Layering - Thermal Oxidation SiO2 functions: Diffusion barrier Surface passivation Field oxide MOS Gate oxide Natural oxide: silicon will readily grow an oxide (5-10nm) if exposed to oxygen in the air! The range for useful oxide thickness: 25nm (MOS gates) - 1500nm (field oxide) Dry oxidation Si + O2  SiO2 (900-1200°C) 700nm oxide: 10hours (1200°C) Good oxide quality: gate oxide O2 Silicon SiO2 Wet oxidation (water vapor or steam) Si + H2O  SiO2 + 2H2 (900-1200°C) 700nm oxide: 0.65hours (1200°C) Poor oxide quality: field oxide

HIGH K MATERIALS

IMPLANTATION/DIFFUSION Doping of silicon is done through implantation. Wells, source-drain regions and poly doping is done through ion implantation and diffusion. Present day processes have very small thermal budget. The source – drain junctions are very shallow. Rapid thermal processing is the most preferred technique for implant activation With very shallow junctions contact formation becomes a very serious problem.

Ion Implantation

Ion-Implantation and Drive-in S/D Formation, Well in CMOS VT adjustment, Punch-through implant 98

Advantages of Ion Implantation over Diffusion Control over amount of dopant introduced Isotropy of Diffusion Implantation allows for multiple implants Implantation ensures purity of dopant due to mass separation High Vacuum reduces possibility for contamination Implantation - possible at reduced temperatures Implantation doping more uniform as compared to Diffusion

Ion Implantation Process Ionization of dopant source Acceleration through high voltage field Projection of ions towards substrate Injection of ions into substrate Objectives Implantation of specific quantity of dopant Implantation at desired depth Restriction of dopant to desired boundaries Minimization of damage done in the process Applications Source for doping atoms Introduction of a layer of different composition into layer

Photoresist UV light sensitive organic material Two types of resist Positive resist: UV light breaks it down Negative resist: UV light hardens it Selectively expose through a mask Develop desired areas by heating harden or breakdown Remove unwanted resist use weak organic solvent Photoresist SiO2 silicon wafer UV light mask

Etching Selectivity Yellow: layer to be removed; blue: layer to remain A poorly selective etch removes the top layer, but also attacks the underlying material. A highly selective etch leaves the underlying material unharmed.

Etching Isotropy Red: masking layer; yellow: layer to be removed A perfectly isotropic etch produces round sidewalls. A perfectly anisotropic etch produces vertical sidewalls.

Material to be Etched Wet Etchants Plasma Etchants silicon (Si) nitric acid (HNO3) + hydrofluoric acid (HF) CF4, SF6, NF3, Cl2, CCl2F2 silicon dioxide (SiO2) hydrofluoric acid (HF) buffered oxide etch [BOE]: ammonium fluoride (NH4F) and hydrofluoric acid (HF) CF4, SF6, NF3 silicon nitride (Si3N4) 85% phosphoric acid (H3PO4) at 180 °C aluminum (Al) 80% phosphoric acid (H3PO4) + 5% acetic acid + 5% nitric acid (HNO3) + 10% water (H2O) at 35-45 °C Cl2, CCl4, SiCl4, BCl3

Mask making Traditionally a lithographic process Rectangles are `flashed' onto photographic plate Mechanical alignment limits precision Electron beam techniques Now widely used Write each pixel sequentially Both techniques generate a reticle Typically 10X larger than final size 10X reticle produces final mask Step-and repeat process 10X reticle Mask

Mask making, cont. Modern processes reaching limits of UV light Extended use of e-beam techniques direct write on wafer X-ray lithography smaller wave lengths much greater cost Advanced techniques have extended the limits Destructive interference Allows much finer features using UV light

LITHOGRAPHY Optical lithography has been holding well steppers have replaced conventional aligners for quite some time I-LINE (365 nm) DUV (248 nm) ArF(193nm) F(157nm) New Lens Material, New Resist Material sub-wave length resolution for 180 nm and smaller features will require advanced mask technologies Multi-layer resist process.

DEPOSITION – POLY SILICON GATE Doped poly silicon which provides self aligned gate structures has a good work function matching with the substrate and allows subsequent high temperature processing. This has been the choice as the gate electrode for a very long time. Poly silicon and oxide layers are deposited through cvd/lpcvd processes. Implant doped poly ( n+ n channel side and p+ on p channel side capped with silicides is the present gate electrode.

Chemical Vapor Deposition (CVD) Deposited materials: Insulators & Dielectrics: SiO2, Si3N4, Phosphorus Silicate Glass (PSG), Doped Oxide Semiconductors: Si Conductors: Al, Ni, Au, Cr, doped polysilicon Basic CVD processing: a gas containing an atom(s) of the material to be deposited reacts with another gas liberating the desired material the freed material (atom or molecular form) “deposits” on the substrate the unwanted products of the chemical reaction leave the reaction chamber Ex.: CVD of silicon from silicon tetrachloride SiCl4 + 2H2  Si + 4HCl wafer

METALLIZATION Aluminum alloys have been standard choice for interconnect metal for a long time. Aluminum has been contacting directly the silicon in the earlier processes. Barrier layers have been used for making contacts in fine geometry process to the shallow junctions. The Main Problem Of The Aluminum Metallization Scheme Is Electro-migration Copper is being used increasingly for the interconnect metal at higher levels because of its low conduct ivy and less electromigration sensitivity.

Metalization Cover wafer with SiO2 Typically using CVD Etch oxide for contacts Either poly or diffusion Sputter on metal Aluminum Tungsten Recently, copper Etch away excess metal leaving wires p-WELL n+ p+ n-SUBSTRATE

PLANARIZATION AS THE LAYERS ON A WAFER BUILD UP THE SURFACE MORPHOLOGY BECOMES VERY COMPLEX WITH LOTS OF UPS AND DOWNS, ESPECIALLY WITH THE MULTI LAYER PROCESSES. THIS COMPLICATES THE PHOTOLITHOGRAPHIC PROCESS AS THE LITHO TOOLS HAVE LIMITED DEPTH OF FIELD. THE IMAGE TRANSFER WILL NOT BE PROPER. TO AVOID THESE PROBLEMS THE SURFACE NEEDS TO BE MADE PLANAR. In the early years the popular planarization technology used was based on etch back in which a layer of photo resist is deposited and etched with a low selectivity etch process. The present day processes mostly use cmp (chemical mechanical planarization) techniques for planarization. Metal plugs of refractive metals formed by cvd are used as contact plugs.

Yield

Defects a is approximately 3

Why VLSI? Integration improves the design Lower parasitics = higher speed Lower power consumption Physically smaller Integration reduces manufacturing cost - (almost) no manual assembly

Try Hard for what you want to get…. Otherwise you will be forced to like what you get…….