Microcontroller Enhancement Design Project Abstract End-Product Description The purpose of this project is to investigate, design, test, document and fabricate an application specific integrated circuit that acts as the primary controller of a data recording device. The goal of this project is to investigating new features such as on-chip flash and SRAM, low operating voltage, and improved peripherals. The achievement of the goals of the project will increase the overall performance, decrease power dissipation, add more features, and cut costs. Each of these modifications will help open up new markets for the product. When finished, this product will be a custom microcontroller that is used in an existing data recording product line (DataBridgeTM). The microcontroller will be optimized for the DataBridgeTM product line, reducing the cost of the device while substantially improving its performance. The DataBridgeTM product line allows users to record data from any RS-232 compatible device and easily transfer that data onto a Windows compatible machine. Introduction Technical Approach Background Information Currently, Acumen Instruments Corporation is using an off-the-shelf microcontroller to implement their DataBridge™ line of data recording devices. However, this microcontroller does not meet their need to expand the capability of their DataBridge™ products to open up new marketing opportunities. This project aims to create a custom chip that expands the functionality, increases performance, and lowers the cost of their primary controller used in the DataBridge™ line. The project will be divided into components that can be implemented independently and then later combined to create the final product. Communication between the individuals will be critical since the components must know how to interface with each other. Testing Approach Technical Problem Creating a custom chip profitably while still meeting required specifications is the primary concern. Getting a custom chip fabricated is very expensive, which stresses the importance of thoroughly testing the design to get a correctly working chip with as few fabrications as possible. Initially, the Verilog design will be tested through software simulations. Once the final schematic for the design is obtained, a software test of the system’s timing will be performed. After the layout of the chip is finished, a software test of the timing and correctness of the final layout will occur. The next testing phase will happen once the fabricated chip is received back from MOSIS. Then a comprehensive functionality test will be performed to ensure the product meets specifications. Intended users and uses The end product will have two primary uses. Industrial, medical, and engineering firms will use this product to bridge the gap between their data generating hardware and their data-analyzing computers. Secondly, other customers will use the device to add secondary storage capability to an existing product. Acknowledgement The client of this project, Acumen Instruments Corporation, generously provides all the equipment, financial aid, and technical advice. Xilinx FPGA board Xilinx Foundation Software (FPGA programmer and verilog simulator) Verification circuit The cost of making poster The cost of fabrication of final design (MOSIS) Assumptions Very high performance not necessary (above 40MHz) Dry operating environment Minimal power supply spiking Properly working FPGA and FPGA software Limitations Low budget for upfront costs Die size less than 9 mm2 Power consumption less than 250 mW Must communicate with all RS-232 compatible equipment Design Requirements Design Objectives Code compatible with current microcontroller More memory Improved peripherals More input and output pins 3.3 Volt operations Explore and evaluate other improvements and implement where possible Functional Requirements Read data from existing RS-232 compatible devices Store data on standard secondary media Store data in Windows compatible format Design Constraints Product must operate at a reasonably high frequency (~40 MHz) Product must have low power consumption Milestones Financial and Personnel Budget Ratio of operating voltage to desired operating voltage (Ideally 1). Ratio of memory to desired amount of memory (Ideally 1). Ratio of new communications speed to old communications speed (Ideally 10). Ratio of I/O pins to old I/O pins (Ideally 2). Number of additional features implemented. (Larger is better). Financial Budget Description Cost (US$) Fabrication of Final Design (MOSIS) 10,000.00 Xilinx Spartan FPGA Test Board 1,500.00 Xilinx Foundation Software 5,000.00 Verification Circuit 2,500.00 Project Poster 50.00 TOTAL 19,050.00 Personnel Budget Team Member Hours Seth Allen Hendrickson 120 Kyaw Kyaw 124 Luping Zhou 108 TOTAL 352 Project Team Information Design Team : Dec02-14 Client Advisors Seth Allen Hendrickson sethh@iastate.edu Computer Engineering Acumen Instruments Corporation Dr. Randall L. Geiger rlgeiger@iastate.edu Kyaw Kyaw kkyaw@iastate.edu Electrical Engineering N. Loop Drive, Ames IA 50010 Dr. John W. Lamont jwlamont@iastate.edu Luping Zhou zlp@iastate.edu Computer Engineering www.acumeninstruments.com Ralph E. Patterson III repiii@iastate.edu