Ashley Greenall The University of Liverpool SLHC Hybrid Ashley Greenall The University of Liverpool WP4 SLHC Upgrade Hybrid, Cambridge 2nd August 2007

WP4 SLHC Upgrade Hybrid, Cambridge 2nd August 2007 SLHC Hybrid Outline Wish list, what we would like of the hybrid Hybrid/module concept What we have recently learnt (and implications) ASIC related (die size, pad layout, bonding to the sensor ) Module data/clock rates (their impact on the hybrid layout) Hybrid layout What has to be considered and why WP4 SLHC Upgrade Hybrid, Cambridge 2nd August 2007

WP4 SLHC Upgrade Hybrid, Cambridge 2nd August 2007 SLHC Hybrid Statement from ASIC designers (ABCN Design Preview, W. Dabrowski, 7 March 2007) We design the chip for stable operation at any threshold setting. Instabilities observed usually at very low thresholds are only partially related to the chip design and are mostly related to the hybrid/module design. Imperative that the hybrid be designed using ‘best practices’ to ensure stable operation WP4 SLHC Upgrade Hybrid, Cambridge 2nd August 2007

WP4 SLHC Upgrade Hybrid, Cambridge 2nd August 2007 Hybrid wish list What we would like… A hybrid with minimal area Hence reduced material Populated with a ‘large’ number of readout ASICs (up to 40 off) Ability to wire bond directly from readout ASIC to sensor – eliminates the need for pitch adaptors Designed to match to a single sensor of 99mm x 99mm Operation offers immunity to differing power schemes (serial or parallel (DC-DC converters) Also need to consider: A hybrid layout, which has to take into account The use of low impedance Power and Ground planes to ensure reduction of high frequency parasitics Can manifest itself as capacitive coupling, crosstalk etc. Implies more material(?) Board level high speed transmission line effects Chip-to-package effects (bond pads, bond wires) Series inductance (ground bounce) WP4 SLHC Upgrade Hybrid, Cambridge 2nd August 2007

Hybrid/module concept 99mm 24mm Detail (provisional) 2 ‘fingers’ per hybrid populated with 2 columns of 10 ASICs (40 ASICs total) Electrically one item (maybe) 4 Cu Layers with Kapton dielectric (example from LHCb VELO) 100µm track and gap, 300µm vias (conservative design to maximise yield) 2 x Outer layers (routing) are 5µm Cu with additional ~8µm plating 2 x Inner planes (PWR/GND) are 12µm Cu 50µm Bond Ply (Espanex) between layers 200µm total build thickness Power/Aux Connector offset to allow module mounting back-to-back Connector detail not finalised but could consider using a ZIF type Readout ASICs 99mm SENSOR HV MCC Digital I/O 74mm Power Regulation Power/Aux Bus MCC: Module Controller Chip WP4 SLHC Upgrade Hybrid, Cambridge 2nd August 2007

What we currently know (ASIC die size) The ABCN die size is now ‘fixed’ at 7.5mm x 8.2mm Width is set to 7.5mm, 8.2mm length could still change 7.5mm width allows direct ASIC-to-Sensor bonding Need to constrain the ASIC-to-Sensor wire-bonding angle to ≤ 17° (see next slide) Bonding test plates have been manufactured to check bonding angle envelope (c/o Jeff Bizzell) Emulates various ASIC/Sensor bond pad geometries 2 rows of 64 bond pads with differing bond angles (14° to 28°), see below Will be distributed to those who want them (10 off exist?) WP4 SLHC Upgrade Hybrid, Cambridge 2nd August 2007

What we currently know (bonding angle) cf Tim Jones ABCN Front-end bond pads are now currently ~90µm x 180µm (13 July ’07) But this will leave 20µm separation between the pads – is this sufficient? Originally spec’d 55µm width pads – this results in 60µm separation WP4 SLHC Upgrade Hybrid, Cambridge 2nd August 2007

What we currently know (ASIC-to-sensor detail) For the proposed ASIC die size of 7.5mm x 8.2mm ASIC-to-sensor bonding is achievable With the following provisos 55µm ASIC input bond pad pitch 75.6µm Sensor pitch <17° bonding angle ASIC-to-ASIC separation is 2.1mm For front-end decoupling Miniature capacitor could be placed in this gap 100nF, X7R, 0402 type SMD (Murata…) 1mm x 0.5mm x 0.5mm (L,W & H) Front-end Decoupling Capacitor 16.6° bond angle WP4 SLHC Upgrade Hybrid, Cambridge 2nd August 2007

What we currently know (ASIC detail) Opportunity to also consider optimising ASIC bond pad placement ‘Old’ ABCD Routing “Revised” ABCN Routing Data & Token Pads moved to side Allows direct wire-bonding ByPass routing on chip Reduces hybrid trace routing ABCD ByPass Hybrid Traces Data & Token Passing wire bonds ByPass routing (on chip) Data & Token Passing Hybrid Traces WP4 SLHC Upgrade Hybrid, Cambridge 2nd August 2007

What we currently know (Data rates) Strip Data Rates (Tony Weidberg) Assume module is composed of 4 columns of 10 ABCNs Readout of ABCNs at 10Mbits/s into MCC, offload data at 160Mbits/s Results in little deadtime at expected occupancies – limited safety factor Therefore Plan to increase ABCN readout speed to 80Mbits/s Increase (single) MCC speed to 320Mbits/s Consider operate 2 x MCCs at 160Mbits/s (adds redundancy to readout)? Furthermore New proposal for module operation at 160MHz clock frequency Uses new Command line protocol (CMDII – interleaved SYNC/L1/CMD) See next page… Impacts on hybrid layout (see later) WP4 SLHC Upgrade Hybrid, Cambridge 2nd August 2007

SLHC Module Readout/CMDII (Mitch Newcomer) WP4 SLHC Upgrade Hybrid, Cambridge 2nd August 2007

SLHC Module Readout/CMDII cont’d WP4 SLHC Upgrade Hybrid, Cambridge 2nd August 2007

CMDII – Hybrid Layout (1) With new interleaved command protocol SLHC hybrids may operate with clocks at 160MHz Plus may have to consider off module data rates of up to 320MHz As a rule controlled impedance design should be adopted for switching frequencies ≥100MHz Any mismatch in impedances will result in lower noise immunity (i.e. bit errors) Traces should be considered as transmission lines if their length satisfies the following Critical Length, L>LTr/6 where LTr = Tr/ Td LTr= Length of rising edge Tr= Signal rise time (250ps for ABCN LVDS circuits) Td= Propagation delay/unit length (1.8ns/ft) LTr/6 = 42/6 = 7mm i.e. traces >7mm must be considered as transmission lines For the SLHC hybrid CLK trace length could be ≥100mm Transmission line design has to be adopted Needs verification WP4 SLHC Upgrade Hybrid, Cambridge 2nd August 2007

CMDII - Hybrid Layout (2) Furthermore, The hybrid design and interconnect selection need to be able to operate at the highest frequency component that is present This is related to the rise/fall time of digital edges, not the clock rate! For most applications, the following can be applied: Fk = 0.5/Tr Fk= freq. below which most energy concentrates Tr = pulse rise time (250ps for ABCN LVDS circuits ) Fk = 2GHz Whereas, for the ABCD3T, Tr = 1ns; Fk = 0.5GHz Hybrid requires a flat frequency response of up to 2GHz to be able to pass digital signals with little distortion WP4 SLHC Upgrade Hybrid, Cambridge 2nd August 2007

CMDII - Hybrid Layout (3) Controlled impedance design of hybrid Why? All ABCN fast I/O signalling uses the LVDS standard (with sub-nanosecond transitions) Recommended termination for ‘standard’ LVDS should be in the range 90Ω to 110Ω Hybrid tracking should be designed to ‘match’ this impedance Necessary to maintain integrity of digital signalling Trace critical length is 7mm (traces have to be treated as transmission lines) Typically, for PCBs, the following transmission line geometries are used (diagram shows layouts for differential traces – applicable to LVDS) Which geometry is best suited? Conductors Conductors Dielectric Ground plane Ground plane 1) Edge coupled micro-strip 2) Edge coupled strip-line WP4 SLHC Upgrade Hybrid, Cambridge 2nd August 2007

CMDII - Hybrid Layout (4) Controlled impedance design of hybrid (LVDS Bus routing) Based on ‘thin’ finger geometry (24mm width) Hybrid width available for trace/bus routing is ≤4.5mm Compare with existing Barrel hybrid, for a single row of ASICs, hybrid width available ~6mm Safe(?) to assume that ABCN pad layout will be similar to that of the ABCD Present Barrel and Endcap hybrids have LVDS bus traces routed on inner layers Facilitates layout of ABCN bonding pads whilst maintaining uniform structure of buses Not obvious how we could change this approach Implies that edge coupled strip-line geometry be adopted – bus lines buried on inner layers Hybrid Layout Using the LHCb Velo build: 100µm track and gap, 12µm Cu thickness and 50µm dielectrics Zdiff ~ 52Ω (LVDS requires 90Ω < Zdiff<110Ω) To obtain 100Ω would require either 50µm dielectrics with 40µm track and gap 125µm dielectrics with 100µm track and gap For high yield and low cost, standard capability is 100µm track and gap with 50µm dielectrics – results in impedance mismatch 4.5mm Not possible 24mm WP4 SLHC Upgrade Hybrid, Cambridge 2nd August 2007

CMDII - Hybrid Layout (5) To summarise Maintaining the present strip-line geometry and making use of thin dielectrics may result in signal distortion 50µm thin dielectrics on the hybrid result in high capacitance (~25pF) on a ~100mm trace which will load driver circuits Not possible to obtain transmission line performance LVDS drivers will see a reactive load rather than resistive Differential impedance, Zdiff, is essentially a fixed parameter determined by the dielectric thickness Effective impedance could be further reduced due to uniform loading (capacitive) on the traces What does this mean? Ideally would like to match trace impedance to LVDS termination Currently trace impedance is ~52Ω, we need to match into ~100Ω PCB fabricators quote, typically, controlled impedance tolerances of ±10% A 10% error in transmission line impedance produces a 5% reflection (cf Howard Johnson ‘High Speed Digital Design’) Currently ~50% mismatch resulting in ~25% reflection (this excludes any other inevitable parasitic effects) Can manifest itself as either ringing, overshoot or undershoot of the switching signals resulting in mis-clocking, bit errors etc. Maybe we should consider: Retaining the present layout and reducing the LVDS termination to 50Ω (is this possible?) Change to micro-strip geometry (Zdiff ~85Ω, using standard build), but… Not easy to route! Incurs ‘long’ Cu traces which have to be Nickel-Gold plated (for wire bonding). Addition of Nickel introduces increased losses, due to the skin effect most of the high frequency current will flow through the more ‘resistive’ Nickel plated onto the Cu. At 1GHz, the resistive loss of Nickel is approx. three times greater than that of Cu! (cf Polar Instruments) To mitigate this effect would require selective plating of the bond pads – not obvious how this can be done. LHCb Velo see evidence of this operating at 40MHz on their analogue data streams WP4 SLHC Upgrade Hybrid, Cambridge 2nd August 2007

Power Planes - Hybrid Layout Single finger routing density Power Planes – is there an issue? Ideally would like to restrict the amount of material used in the hybrid build This could compromise the Power/Ground planes (increased impedance) Might also impact upon the module’s stability For present SCT hybrids Barrel hybrid has 2 planes of ~3178mm2 Cu area/plane & 1.6A total current Endcap hybrid required 4 dedicated power planes of ~2500mm2 Cu area/plane (to ensure stable operation) For the SLHC hybrid The hybrid has ~2376mm2 Cu area/plane per finger with 2.74A current (nominal) Based on 4 layer build (2 power/Ground planes) ~70% increase in current with ~25% reduction in Cu (compared to Barrel) Increasing finger width from 24mm to 32.5mm, Cu area becomes comparable to Barrel But still 70% more current! Add more Cu (by increasing Cu thickness/more layers) – to lower plane impedances But Need to consider skin effect Increasing Cu thickness does not necessarily help – only increased Cu area (6 layer build, based on 24mm finger width) Top Layer Inner Layer WP4 SLHC Upgrade Hybrid, Cambridge 2nd August 2007

WP4 SLHC Upgrade Hybrid, Cambridge 2nd August 2007 SLHC Hybrid Summary ASIC width has now been optimised to match the sensor geometry Width set to 7.5mm but still some uncertainty with the length (currently 8.2mm) Facilitates the direct bonding from ASIC-to-sensor Minor optimisation of ASIC bond pad placement has occurred It all helps! Proposal of new command line protocol is significant Requires use of high frequency clock (160MHz) High speed transmission line effects have to be taken into account Hybrid layout and build is now more critical – to maintain signal integrity Not obvious if this is achievable or what the outcome will be Do we really need this new protocol? Does the present geometry compromise stable operation? 70% increase in current with 25% less Cu available Do we need more layers or will it be necessary to increase the hybrid finger widths? WP4 SLHC Upgrade Hybrid, Cambridge 2nd August 2007