A MIPS R2000 Implementation

Slides:

Advertisements

Similar presentations

Introduction to Programmable Logic John Coughlan RAL Technology Department Electronics Division.

Advertisements

Final Project : Pipelined Microprocessor Joseph Kim.

August 8 th, 2011 Kevan Thompson Creating a Scalable Coherent L2 Cache.

ARM Cortex-A9 MPCore ™ processor Presented by- Chris Cai (xiaocai2) Rehana Tabassum (tabassu2) Sam Mussmann (mussmnn2)

The Raw Architecture Signal Processing on a Scalable Composable Computation Fabric David Wentzlaff, Michael Taylor, Jason Kim, Jason Miller, Fae Ghodrat,

Jared Casper, Ronny Krashinsky, Christopher Batten, Krste Asanović MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA, USA A Parameterizable.

Pentium microprocessors CAS 133 – Basic Computer Skills/MS Office CIS 120 – Computer Concepts I Russ Erdman.

The Stanford Smart Memories: A 90nm, 55M transistor, 61mm², 8-core chip multiprocessor VLSI technology scaling is driving changes Designs are getting complex.

CPU Processor Speed Timeline Speed =.02 Mhz Year= 1972 Transistors= 3500 It takes 66, CPU’s to equal 1 i7.

7/14/2000 Page 1 Design of the IRAM FPU Ioannis Mavroidis IRAM retreat July 12-14, 2000.

The Design Process Outline Goal Reading Design Domain Design Flow

Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007.

Physical Design Outline –What is Physical Design –Design Methods –Design Styles –Analysis and Verification Goal –Understand physical design topics Reading.

S. Reda EN1600 SP’08 Design and Implementation of VLSI Systems (EN1600) Lecture 24: Computer-Aided Design using Tanner Tools Prof. Sherief Reda Division.

DATA ACQUISITION SYSTEM FPGA2 APEX20K200E SAMSUNG MICROCONTROLLER ARM - RISC CORE (50MHZ – 32 BIT, 8 KByte SRAM) BOOT FLASH 512K X 16 PROGRAM MEMORY SDRAM.

Final Exam Review B. Ramamurthy. Date, Time and Place Date: Tuesday May 5, 2009 Time: AM Place: Filmore 170 Please bring pens, pencils, calculator.

Introduction to CMOS VLSI Design Case Study: Intel Processors.

A Flexible Architecture for Simulation and Testing (FAST) Multiprocessor Systems John D. Davis, Lance Hammond, Kunle Olukotun Computer Systems Lab Stanford.

Dept. of Communications and Tokyo Institute of Technology

DOP - A CPU CORE FOR TEACHING BASICS OF COMPUTER ARCHITECTURE Miloš Bečvář, Alois Pluháček and Jiří Daněček Department of Computer Science and Engineering.

CAD for Physical Design of VLSI Circuits

AT94 Training 2001Slide 1 AT94K Configuration Modes Atmel Corporation 2325 Orchard Parkway San Jose, CA Hotline (408) OR.

Introduction to CMOS VLSI Design Lecture 22: Case Study: Intel Processors David Harris Harvey Mudd College Spring 2004.

Introduction to VLSI Design – Lec01. Chapter 1 Introduction to VLSI Systems Lecture # 10 MIPS Processor Example Material taken/adapted from.

SPREE RTL Generator RTL Simulator RTL CAD Flow 3. Area 4. Frequency 5. Power Correctness1. 2. Cycle count SPREE Benchmarks Verilog Results 3. Architecture.

CPE 626 Advanced VLSI Design Aleksandar Milenkovic Assistant.

1 Towards Optimal Custom Instruction Processors Wayne Luk Kubilay Atasu, Rob Dimond and Oskar Mencer Department of Computing Imperial College London HOT.

Chonnam national university VLSI Lab 8.4 Block Integration for Hard Macros The process of integrating the subblocks into the macro.

Computer Organization and Architecture Tutorial 1 Kenneth Lee.

VLIW Digital Signal Processor Michael Chang. Alison Chen. Candace Hobson. Bill Hodges.

Lecture 2: MIPS Processor Example

FPGA-based Fast, Cycle-Accurate Full System Simulators Derek Chiou, Huzefa Sanjeliwala, Dam Sunwoo, John Xu and Nikhil Patil University of Texas at Austin.

IMPLEMENTATION OF MIPS 64 WITH VERILOG HARDWARE DESIGN LANGUAGE BY PRAMOD MENON CET520 S’03.

Computer Architecture Introduction Lynn Choi Korea University.

CMOS VLSI Design MIPS Processor Example

Chap 4: Processors Mainly manufactured by Intel and AMD Important features of Processors: Processor Speed (900MHz, 3.2 GHz) Multiprocessing Capabilities.

High-Bandwidth Packet Switching on the Raw General-Purpose Architecture Gleb Chuvpilo Saman Amarasinghe MIT LCS Computer Architecture Group January 9,

Real-Time System-On-A-Chip Emulation.  Introduction  Describing SOC Designs  System-Level Design Flow  SOC Implemantation Paths-Emulation and.

Application-Specific Customization of Soft Processor Microarchitecture Peter Yiannacouras J. Gregory Steffan Jonathan Rose University of Toronto Electrical.

Microprocessor Design Process

Lecture 4: Contrasting Processors: Fixed and Configurable September 20, 2004 ECE 697F Reconfigurable Computing Lecture 4 Contrasting Processors: Fixed.

IMPLEMENTING RISC MULTI CORE PROCESSOR USING HLS LANGUAGE - BLUESPEC LIAM WIGDOR INSTRUCTOR MONY ORBACH SHIREL JOSEF Winter 2013 One Semester Mid-term.

VLSI Design Flow The Y-chart consists of three major domains:

ALPHA 21164PC. Alpha 21164PC High-performance alternative to a Windows NT Personal Computer.

SPRING 2012 Assembly Language. Definition 2 A microprocessor is a silicon chip which forms the core of a microcomputer the concept of what goes into a.

Itanium® 2 Processor Architecture

Differencing Multistage Detector

David Harris Harvey Mudd College Spring 2004

ELEC 7770 Advanced VLSI Design Spring 2016 Introduction

VLSI Testing Lecture 5: Logic Simulation

R&D activity dedicated to the VFE of the Si-W Ecal

Application-Specific Customization of Soft Processor Microarchitecture

Hugo França-Santos - CERN

SmartCell: A Coarse-Grained Reconfigurable Architecture for High Performance and Low Power Embedded Computing Xinming Huang Depart. Of Electrical and Computer.

AndesCoreTM N1213-S

ELEC 7770 Advanced VLSI Design Spring 2014 Introduction

A Review of Processor Design Flow

Figure 13.1 MIPS Single Clock Cycle Implementation.

ELEC 7770 Advanced VLSI Design Spring 2012 Introduction

ELEC 7770 Advanced VLSI Design Spring 2010 Introduction

VLIW DSP vs. SuperScalar Implementation of a Baseline H.263 Encoder

A High Performance SoC: PkunityTM

HIGH LEVEL SYNTHESIS.

第四章 80386的存贮器和输入/输出接口作业：P335 5,7,13,17,21,25,36,37,41,44,45,46,48,52,65 21:46.

Introduction to VLSI Design Logic Arrays

Learning Objectives To be able to describe the purpose of the CPU

Arithmetic Building Blocks

Application-Specific Customization of Soft Processor Microarchitecture

B9 Reid Long, Teguh Hofstee

Presentation transcript:

A MIPS R2000 Implementation Introductory CMOS VLSI class Undergraduates: 30 at HMC, 4 at U of Adelaide Microarchitecture Five-stage pipeline and hazard/exceptions units Booth-encoded, radix-4 multiply/divide unit 512 byte I-/D-caches in core, 4 entry write-buffer Project Partitioning Clusters Microarchitecture (RTL) Chip (datapath, control, memory, COP0) Systems (compiler, FPGA emulation, PCB) Library (Std. cells, PLA) Schematics/layout in Electric Custom PLA generator

Fabrication Verification DRC/NCC/ERC in Electric Ad-hoc Verilog behavioral Random test vector generation IRSIM switch-level simulations Single-/dual-FPGA emulation Fabrication CIF generated by Electric AMI Mosis 0.5-mm, 4.5 mm 160k transistors 108-pin PGA

Testing/Performance Performance 7.25 MHz, limited by caches Processor Vax Score (DMIPS) Clock Speed (MHz) DMIPS /MHz HMC MIPS (cache disabled) 0.36 7.25 0.050 1.08 0.150 DECstation 2100 R2000 11.193 12 0.93275 SGI Personal Iris 4D/20 R2000 9.812 12.5 0.78496 Performance 7.25 MHz, limited by caches Power is 52 mW @ 7.25 MHz More Information http://www4.hmc.edu:8001 /Engineering/158/07/project