Complex and Reduced Instruction Set Computers CISC and RISC Complex and Reduced Instruction Set Computers Copyright © 2005-2007 – Curt Hill
Copyright © 2005-2007 – Curt Hill A little history: The development of CPUs like all good developments is subject to different (even conflicting) pressures The direction that these pressures push CPUs is the story behind CISC vs RISC During 60's and 70's one of the determining factors of computers was the high cost of memory It was to the advantage of the CPU designer to optimize the CPU for the use of memory Copyright © 2005-2007 – Curt Hill
Efficient Use of Memory This can only really be accomplished by one of two techniques: Compress your instructions or data Make your instruction set extremely clever so that your programs fit into the smallest space Compress your data in some fashion Though this is an important aspect it is usually not handled by the chip level design - hence only the first is handled by CPU designers Copyright © 2005-2007 – Curt Hill
Copyright © 2005-2007 – Curt Hill Optimization Therefore during 60's and 70's people optimized new CPU designs towards making the programs as compact as possible The exception to this trend was Seymour Cray, who was mainly interested in raw speed This was done by making your instruction set much more complex: Adding additional addressing modes Making single instructions of what used to be subroutines The translate instruction or Edit of 370 By the time that IBM had passed the 370 and was into the 3000, they were taking system subroutines and making them into single instructions Copyright © 2005-2007 – Curt Hill
Copyright © 2005-2007 – Curt Hill MicroProgramming Facilitated by the introduction of microprogramming In microprogramming each instruction becomes a procedure call The code for the procedure is in the control store (not programmably accessible) Any instruction could be as complicated as you wanted it to be Consider the entry/exit conventions of system 370 Make this a single instruction with a few parameters Copyright © 2005-2007 – Curt Hill
Copyright © 2005-2007 – Curt Hill DEC VAX is the Zenith It has over 200 instructions Dozens of distinct addressing modes Instructions with as many as 6 operands It has a single instruction that evaluates a single variable polynomial, such as: ax3+bx2-cx+d A single instruction that does a procedure call including: Saving a subset of the registers Adjusting the stack pointer Saving return address Jumping to new procedure Many C programs were one to one with the assembly language Copyright © 2005-2007 – Curt Hill
Copyright © 2005-2007 – Curt Hill Tradeoffs In Computer Science there exists the space speed - tradeoff In general any program (or in this case CPU) can be optimized for space or speed It is usually at the expense of the other Eg. data compression conserves space but at the expense of speed Copyright © 2005-2007 – Curt Hill
Copyright © 2005-2007 – Curt Hill Changes However, by the end of the 70's and middle 80's, the winds had changed Integrated circuits sophisticated enough to capture a CPU came about Memory prices dropped faster than CPU prices Now the constraint was not get the most bang for your memory buck, but rather get the most bang for your buck in exploiting the silicon real estate that constitutes a CPU Copyright © 2005-2007 – Curt Hill
Integrated Circuit Real Estate A CISC requires more of that real estate than a RISC So what you do to optimize speed of instructions or reduce the CPU space is to make RISCs Fewer addressing modes, fewer instructions, a tendecy for fixed size instructions rather than variable Copyright © 2005-2007 – Curt Hill
Copyright © 2005-2007 – Curt Hill Examples Reduced Instruction Set Computer PowerPC DEC Alpha MIPS RISC Sun SPARC Intel XEON Complex Instruction Set Computer The Pentium, as well as its predecessors 360/370 VAX Copyright © 2005-2007 – Curt Hill
Copyright © 2005-2007 – Curt Hill CISC They provide a variety of addressing modes and a rich variety of instructions In many respects they are designed to optimize speed and ease of programming However there is a price to be paid for these complications The CPU get very complicated, in the case of single chip CPUs each one has strained our ability to integrate a device that complicated on one piece of silicon It also makes for exciting instruction set design Copyright © 2005-2007 – Curt Hill
Copyright © 2005-2007 – Curt Hill RISC Do not do everything – be simple Keep the instructions simple and the addressing modes simple So we may not have a symmetrical instruction set or be able to do in one instruction what the CISC can Doing in three instructions what a CISC can do in one is OK, if that allows us to have a smaller, fixed length instruction format It is often the case that then the RISC can run at higher speeds and end up with a net gain of speed for programs Copyright © 2005-2007 – Curt Hill
Copyright © 2005-2007 – Curt Hill Competition Intel has been the champion of CISC Their finesse at integration has allowed them to make larger CPUs Others have compensated by making faster and smaller chips Such as PowerPC Copyright © 2005-2007 – Curt Hill
Copyright © 2005-2007 – Curt Hill Hitting the wall Intel in about 1995 determined that heat was limiting what it could do with one CPU Instead of going to a RISC chip, which would forfeit its customer base It decided to go multi-core Two slower CPUs can be put on one chip and run faster than one faster Generate less heat as well Copyright © 2005-2007 – Curt Hill