Atomic Clock Receiver

Team Staff Atomic Clock Receiver Atomic Clock Receiver Expertise: 318-595 Spring 2005, Team #4 Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver Team Staff Michelle Hecyk - BSEE Expertise: PLD, Project Mgmt, Technical Writing Experience: 1 Co-op @ GE Cons & Industrial 2 Co-ops + 1.5 years @ GE Supply Jonathan West - BSEE Expertise: Microwave, VLSI, 6σ, Assembly Experience: 3 Co-ops @ GE Healthcare Ned Storer - BSEE Expertise: Communication, PCB layout Experience: 1.5 years intern @ Wells Mfg 2 Co-ops @ Pentair Water Harrison Chiu - BSEE Expertise: Software Simulation/Testing Experience: Software QA @ JCI for 8mo

Team Affiliations Designed for Pentair Water Treatment Purpose: reset internal clock of water softener when power is lost. Company Contact: Mike Lindfors

Team Dynamics Atomic Clock Receiver Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver Team Dynamics Chose project because it will give us industry experience developing a product for a company given desired product specifications and target cost. Decisions made by consensus Established team website to ease file sharing/storage and communication Regular meetings Monday evenings and Sunday afternoons Responsibilities assigned as follows: Jonathan West: Assembly & Proto Mgr, Archive Web Mgr Ned Storer: Project Integrator Harrison Chiu: PCB Layout Mgr Michelle Hecyk: Report & Presentation Mgr

Team Resources Estimated Hours: 500 hours Actual Hours: 840 hours Estimated development cost: $100.00 Actual development cost: $276.17

Product Purpose Atomic Clock Receiver Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver Product Purpose The purpose of this device is to provide an accurate time signal to an external device upon request. Current applications require manual intervention to re-program correct time after loss of power. This project aims to automate this process, eliminating the need for manual intervention.

Product Functions Atomic Clock Receiver Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver Product Functions Accurate time will be maintained internally by periodically syncing the on-board clock with an atomic clock by means of the NIST radio station: WWVB. A time request from the host system will be fulfilled instantaneously providing date and time (accurate to the second) in military format. Device will be AC powered with battery back-up and run independently of any host system it is connected to. Time output in RS232 format

Competition ClockWatch Radio Sync Broadcast-based timeserver Radio Sync acquires precise time from WWVB radio broadcast Ideal for highly secure or remote installations Can run off of either RS232 or and external source Sold as a bundle with interface software for $199.95

318-595 Spring 2005, Team #4 Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver Product Features Manual Sync Option allows user to update system time on request Optional external serial interface allowing PC hookup System monitor

Requirements Harrison Chiu Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver Requirements Harrison Chiu

Product Standard Requirements Market Geographics Continental USA only Europe and Hawaii possible with slight design modifications Market Demographics Residential, Commercial, and Industrial Applications

Product Standard Requirements Business Case Market Size: $10M Annual Volume: 10,000 List Price: $60.00 Material Cost: $30.00 Mfg Cost: $10.00 Development Costs Engineering: $75,000 Materials: $1,000 Annual Sales: $0.6M Per Unit CM: $20 CM%: 33% Annual CM$: $1M ROI : 0.4 years

Product Standard Requirements User Warnings Intended for use only within the Continental United States Atomic Receiver may not be able to receive a signal in certain locations or during certain times of the day due to weak signal strength. Electrical Shock Hazard! Keep away from liquids and do not try to disassemble this product

Performance Requirements User Interface User Inputs Master Reset Switch Resets product Manual Synch Button Decode WWVB Signal Update Internal Clock User Indicators ACR Receiver Indicators Visually displays incoming WWVB signal (Green) Indicates any errors that occur (Yellow) Power Indicator Red LED Signals circuit is powered

Performance Requirements Operational Modes Power Modes: On Functional Modes Decode WWVB Output Time (upon host unit request) Standby (normal operation mode)

Standard Requirements Power

Performance Requirements Signal Characteristics

Performance Requirements Electrical Transfer Performance

Additional Standard Requirements Manufacturing and Lifecycle

Additional Standard Requirements Mechanical

Additional Standard Requirements Environmental

Product Level Standard Requirements 318-595 Spring 2005, Team #4 Atomic Clock Receiver Product Level Standard Requirements Health & Safety Compliant with the following standards: IEC 60950-1: IT equipment - Safety - Part 1: General Req. UL 1270: Radio Receivers, Audio Systems, and Accessories ISO9001:2000 Quality Management Systems-Requirements Components Minimum lead component usage in product Power Current limiting protected power source Case Plastic case insolated plastic Weather resistance seal on casing Max User surface potential = 0V EMC Standards EN 61000 - General EMC Standard EN 61204-3:2001 - Low Voltage Power Supplies DC Output. (Part 3: Electromagnetic compatibility)

318-595 Spring 2005, Team #4 Atomic Clock Receiver Block Diagram

Block 4 - Power Michelle Hecyk Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver Block 4 - Power Michelle Hecyk

LOCATION ON BLOCK DIAGRAM 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 4 – Power LOCATION ON BLOCK DIAGRAM

DESCRIPTION Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 4 – Power DESCRIPTION Provides DC voltage to all necessary components Converts 120VAC to 3.3VDC Plugs into any standard wall outlet Provides battery back-up in case of power failure Output voltage regulated to ensure maximum performance

PERFORMANCE REQUIREMENTS 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 4 – Power PERFORMANCE REQUIREMENTS Operational Modes User Interfaces

PERFORMANCE REQUIREMENTS 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 4 – Power PERFORMANCE REQUIREMENTS Electrical Interfaces & Power

PERFORMANCE REQUIREMENTS 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 4 – Power PERFORMANCE REQUIREMENTS Safety Ratings Safety & EMC Standards Primary Safety Standards: IEC60950: IT equipment - Safety - Part 1: General Primary EMC Standards: EN61204-3: Low Voltage Power Supplies DC Output (Part 3: Electromagnetic compatibility)

STANDARD REQUIREMENTS 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 4 – Power STANDARD REQUIREMENTS Mechanical and Manufacturing

STANDARD REQUIREMENTS 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 4 – Power STANDARD REQUIREMENTS Environmental

BLOCK DIAGRAM OF BLOCK Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 4 – Power BLOCK DIAGRAM OF BLOCK

Block Schematic Atomic Clock Receiver 318-595 Spring 2005, Team #4 BLOCK 4 – Power Block Schematic

318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 4 – Power AC/DC Converter Block Step-down incoming AC voltage to manageable level Minimize power loss Rectify AC voltage using full wave bridge rectifier Provide low noise output signal

AC/DC Converter Block Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 4 – Power AC/DC Converter Block Transformer Calculations (Minimum): Incoming AC voltage: 102-132V Minimum output required to Main Feeder Block regulator is 4.3VDC Bridge rectifier must be able to supply at least 4.4VDC with 102VAC input Vsec=4.4VDC + 1.4VDC = 4.1VAC 1.414 Accounting for the 1.4V drop across rectifier and the RMS to peak relationship (1.414) we find 5VAC will be sufficient secondary rating. Vo,min=Vi,min = 102VAC = 4.25 * 1.414 = 6VDC N 24 Transformer Calculations (Nominal): Vo,nom=Vi,nom = 120VAC = 5VAC * 1.414 = 7.07VDC

AC/DC Converter Block Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 4 – Power AC/DC Converter Block Transformer Calculations (Maximum): Incoming AC voltage: 102-132V Maximum input voltage to Main Feeder Block regulator is 20VDC Bridge rectifier must not supply more than 20VDC with 132VAC input Using N=24 we find the following: Vo,max=Vi,max = 132VAC = 5.5VAC * 1.414 = 7.77VDC N 24 Over-Current Protection Calculations: F1 = 2*I = 2*.500 = 42mA N 24 To keep standard component values we will use a 1A fuse

AC/DC Converter Block Atomic Clock Receiver Rectifier Calculations: 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 4 – Power AC/DC Converter Block Rectifier Calculations: Diode Specs - PIV (Peak Inverse Voltage) rating of 2.828 x Vsec is desirable 14V is not a standard value so we will use minimum of 35V @ 1A Output Filter Capacitor Calculations: Maximum ripple: 2.5% Vripple=7.77V x 0.025 =.194Vrms Vripple=2.828 x .194V = .549V Time interval for charge pulse: t=1/(2*f)=1/(2*60)=8.3mS To keep standard component values we will use a 6800uF capacitor

Main Feeder Block Atomic Clock Receiver Regulation: 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 4 – Power Main Feeder Block Regulation: Provides 3.3VDC Vdd signal to all blocks Input Voltage Min: 4.3V Output Voltage Range: 3.22 – 3.38VDC Typical Output Voltage Noise: 20uVrms* *when Cout=10uF and Cbyp=.01uF Min Ripple Rejection: 50dB Max ripple rejection accomplished with .01uF bypass capacitor Output capacitor provides improved transient response

Main Feeder Block Battery Back-up Switch: Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 4 – Power Main Feeder Block Battery Back-up Switch: When Vin < 3.0V AND Vin < Vbatt: Vcc switches to battery signal Vout(min)= Vbatt-.2 Iout(max) = 40mA When Vcc returns above 3.0V: Vcc switches to Vin signal Vbatt returns to standby (I =.02uA) BATT ON Logic high when battery on Useful for future applications where battery status information is required

Battery Supply Block House and regulate back-up battery voltage 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 4 – Power Battery Supply Block House and regulate back-up battery voltage (4AA Alkaline Batteries) Provides 3.3VDC signal to Main Feeder Block Input Voltage Min: 4.3V Output Voltage Range: 3.22 – 3.38VDC Typical Output Voltage Noise: 20uVrms* *when Cout=10uF and Cbyp=.01uF Min Ripple Rejection: 50dB Regulator design provides reverse battery protection

Battery Supply Block Battery Life Calculations: Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 4 – Power Battery Supply Block Battery Life Calculations: Using a standard 2500mAh battery we obtain the following results for battery life: BLOCK TYPICAL MAX Signal Receiving 50uA 100uA PIC 500uA 780uA User Int 150uA 300uA Filtering 700uA 1.1mA TOTAL 1.4mA 2.28mA CURRENT DRAW PER BLOCK

Power Block Passive Discrete Specifications 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 4 – Power Power Block Passive Discrete Specifications Component Nominal or Max Value Tolerance Around Nominal Maximum Working Voltage Composition Dielectric or Form Pkg Voltage Regulators Output Capacitor 10uF +/- 20% 10V Alum Electrolytic SMT Bypass Capacitor .01uF +/- 10% 100V Ceramic Input Capacitor 1uF 50V Battery Back-up Switch Decoupling Capacitors .1uF 35V Tantalum Rectifier/Filter Filter Capacitor 6800uF 25V Axial

Bill of Materials Atomic Clock Receiver 318-595 Spring 2005, Team #4 BLOCK 4 – Power Bill of Materials

Manual Manufacturing Processes 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 4 – Power Manual Manufacturing Processes Manual Solder: Voltage Regulator 1 Voltage Regulator 2 Battery Holder Transformer with heat sink Manual Placement: 4AA Batteries in Battery Holder Insert Fuse in Power cable inlet Connect power cable

Manufacturing Test Process 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 4 – Power Manufacturing Test Process Test 1 Primary Power Verification: Action 1: Apply 102VAC Verify: Output voltage 3.1 - 3.5 VDC Action 2: Apply 132VAC Verify: Output voltage 3.1 – 3.5 VDC Test 2 Battery Power Verification: Action 1: Step 1-Apply 120VAC for 10 seconds Step 2-Remove AC Power Action 2: Apply 120VAC

Block Reliability Analysis 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 4 – Power Block Reliability Analysis Dominant parts for unreliability are: Power Transformer and Electrolytic Capacitors Plan for reliability improvement: Switch to higher rated temperature on transformer Switch to ceramic or tantalum capacitors where possible

Sustainability Aspects: Obsolescence 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 4 – Power Sustainability Aspects: Obsolescence Voltage Regulators have smallest Obsolescence Window. Modern technology being used so corrective actions are not required.

Block Requirement Verification 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 4 – Power Block Requirement Verification Block Requirement # Verification Plan Energy Source Input Voltage Range, Current, Frequency 1 Engineering Analysis Lab Test Max Power Consumption, Voltage Ripple, Battery Life 2 Engineering Analysis Lab Test User Interface Operation, Viewing Distance 3 Lab Test Operating and Storage Temp 4 Engineering Analysis Lab Test Max Parts Count, Max PCB Area 5 Engineering Analysis Safety Standards 6 Safety/UL Testing

Amplifier Block Ned Storer

Description Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 1 – Amplifier Description This block is responsible for receiving and amplifying the WWVB signal. It is the first block in the overall block diagram.

Block Performance Requirements 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 1 – Amplifier Block Performance Requirements

Input to Output Requirements Analog Signal Interface Requirements 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 1 – Amplifier Input to Output Requirements Minimum input signal field strength = 100 µV/m Frequency Range = 59.65 to 60.35 kHz Output voltage range = 10 to 3000 mV Maximum output current = 5 mA Analog Signal Interface Requirements Nominal Signal Band-width = 700 Hz Maximum allowable input noise = 100 nV/hz

Block Standard Requirements 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 1 – Amplifier Block Standard Requirements

Performance Requirements 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 1 – Amplifier Performance Requirements Power Input: 3.3 V DC Minimum Input Signal Strength: 100 µV/m Nominal Input Frequency: 60 kHz Bandwidth: 700 Hz Minimum SNR = 40 dB Maximum Power Consumption = 100 mW

Operating & Storage Requirements 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 1 – Amplifier Operating & Storage Requirements Operating Temp Range: 0 to 40 °C Storage Temp Range: -10 to 50 °C Operating Humidity Range: 0 to 90% Storage Humidity Range: 0 to 100% Operating Altitude Range: 0 to 4300 m Storage Altitude Range: 0 to 14000 m Maximum Storage Duration = 5 yrs

Applicable Input Power Special Block EMC Standards 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 1 – Amplifier Applicable Input Power Nominal Input Voltage = 3.3 V DC Input Voltage Tolerance = -0.5V / +0.2V Special Block EMC Standards FCC Part 15 Not allowed to transmit any harmful interference (unintentional transmitter) Must accept any harmful interference received

Mechanical Interfaces Applicable Operational Modes 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 1 – Amplifier Mechanical Interfaces Adhesive for mounting antenna 1.5” of tolerance space given to end for final antenna placement Applicable Operational Modes On

Overall Allocation for Block 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 1 – Amplifier Overall Allocation for Block Maximum total Parts = 8 Maximum unique parts = 4 Maximum component costs = $2.00 Maximum mass of Block = 450 g Maximum PCB area = 1 in2

Block Detailed Design Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 1 – Amplifier Block Detailed Design

Block Diagram Atomic Clock Receiver 318-595 Spring 2005, Team #4 BLOCK 1 – Amplifier Block Diagram

Block Schematic Atomic Clock Receiver 318-595 Spring 2005, Team #4 BLOCK 1 – Amplifier Block Schematic

Design Calculations Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 1 – Amplifier Design Calculations A loop antenna was chosen to be used in this project due to it’s small size and low cost. Assumptions made: Antenna voltage output => V = 10 µV RF field strength => E = 100 µV/m Angle between the plane of the loop and the signal source => θ = 0° Area of loop => A = 0.25 in2 Wavelength of operation => λ = 5000 m Q of loop => Q = 80 Permeability of an available ferrite rod => µrod = 850

318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 1 – Amplifier Design Calculations Equation used to design loop antenna without ferrite core => V = (2π* A * N * E * cos θ) / λ The minimum number of turns required would be: N = 493,381 turns The number of turns that be required are unrealistic, therefore, a ferrite core was decided to be used in the antenna.

Using a ferrite core in the antenna 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 1 – Amplifier Using a ferrite core in the antenna The ferrite core reduces the reluctance of the antenna which increases the amount of flux into the antenna.

318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 1 – Amplifier Design Calculations The equation used to determine the corrected permeability was µ’ = µrod * 3(lcore / lcoil) The corrected permeability equation used is µ’ = 850 * 3(2 / (N * 1.57) The equation used to find the minimum number of turns needed in the antenna is V = (2π * A * N * µ’ * Q * E) / λ The minimum number of turns needed in the antenna is N = 17.3 turns The more turns added to the antenna will increase the output voltage.

Capacitor Specification 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 1 – Amplifier Capacitor Specification All capacitors are ceramic 47nF capacitor 25 V rated ±10% tolerance 10µF capacitor 6.3 V rated ±20% tolerance

Packaging Selection Capacitor Package = > 0805 package 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 1 – Amplifier Packaging Selection Capacitor Package = > 0805 package Crystal Package => Cylinder – 13 IC => SOIC Antenna => no standard package

Power Supply Analysis Output voltage range = 10 to 3000 mV 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 1 – Amplifier Power Supply Analysis Output voltage range = 10 to 3000 mV Maximum output current = 5 mA Maximum allowable noise = 100 nV/hz

Block Manufacturing Aspects 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 1 – Amplifier Block Manufacturing Aspects

Block BOM Atomic Clock Receiver 318-595 Spring 2005, Team #4 BLOCK 1 – Amplifier Block BOM

Block PCB Layout Atomic Clock Receiver 318-595 Spring 2005, Team #4 BLOCK 1 – Amplifier Block PCB Layout

Block Reliability Analysis 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 1 – Amplifier Block Reliability Analysis

Summary Table Atomic Clock Receiver 318-595 Spring 2005, Team #4 BLOCK 1 – Amplifier Summary Table

Overall Block MTBF Total MTBF = 148.23 Yrs 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 1 – Amplifier Overall Block MTBF Total MTBF = 148.23 Yrs Dominant parts for unreliability are: Crystal Receiver IC Plan for reliability improvement: Find a crystal with a higher maximum temperature

Block Obsolescence Table 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 1 – Amplifier Block Obsolescence Table

Obsolescence Analysis 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 1 – Amplifier Obsolescence Analysis MAS 9180 has the greatest chance of becoming obsolete. The part was introduced in February 2005 No corrective actions need to occur at this point.

Block Verifications Atomic Clock Receiver 318-595 Spring 2005, Team #4 BLOCK 1 – Amplifier Block Verifications

Ideal Simulation Results 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 1 – Amplifier Ideal Simulation Results The waveforms below show what an ideal bit from the amplifier output looks like. Start / End / Position Bit Logic “1” Bit Logic “0” Bit

318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 1 – Amplifier Sample Ideal Signal The waveform below is an illustration of the first ten bits of the ideal signal “…11101100000100...” would look like.

Block 2 - Filtering Jonathan West Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver Block 2 - Filtering Jonathan West

Atomic Clock Receiver Block 2: Filtering Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter Atomic Clock Receiver Block 2: Filtering

Block 2: Function and Purpose 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter Block 2: Function and Purpose Receives noisy, amplified signal from Block 1 Filter out all unwanted noise from signal Feed clean signal to the Microcontroller Provide Stable Voltage Reference for A/D Conversion

Block 2 Requirements Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter Block 2 Requirements

Block 2 Performance Reqs 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter Block 2 Performance Reqs

Block 2 Performance Reqs 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter Block 2 Performance Reqs

Block 2 Standard Requirements 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter Block 2 Standard Requirements Power

Block 2 Standard Requirements 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter Block 2 Standard Requirements Mechanical

Block 2 Standard Requirements 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter Block 2 Standard Requirements Manufacturing and Lifecycle

Block 2 Standard Requirements 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter 318-595 Spring 2005, Team #4 Atomic Clock Receiver Block 2 Standard Requirements Safety Health & Safety Compliant with the following standards: IEC 60950-1: IT equipment - Safety - Part 1: General Req. UL 1270: Radio Receivers, Audio Systems, and Accessories ISO9001:2000 Quality Management Systems-Requirements EMC Standards EN 61000 - General EMC Standard

Block 2 Detailed Design Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter Block 2 Detailed Design

Block 2: Block Diagram Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter Block 2: Block Diagram

Block 2: Schematic Atomic Clock Receiver 318-595 Spring 2005, Team #4 BLOCK 2 – Filter Block 2: Schematic

Block 2: Design Calculations 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter Block 2: Design Calculations Delyiannis-Friend Transfer Function Of the Form:

Block 2: Design Calculations 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter Block 2: Design Calculations Delyiannis-Friend Nominal Values Let Ho=10 and C=1nF

Block 2: Stage 2 Design Calculations 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter Block 2: Stage 2 Design Calculations

Block 2: Overall Gain vs Frequency Response 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter Block 2: Overall Gain vs Frequency Response

Block 2: Monte Carlo Gain Analysis 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter Block 2: Monte Carlo Gain Analysis Resistor Tolerance: 1% Capacitor Tolerance: 10%

Block 2: Monte Carlo Gain Analysis 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter Block 2: Monte Carlo Gain Analysis Resistor Tolerance: 1% Capacitor Tolerance: 10%

Block 2: Monte Carlo Phase Analysis 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter Block 2: Monte Carlo Phase Analysis Resistor Tolerance: 1% Capacitor Tolerance: 10%

Block 2: Voltage Reference 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter Block 2: Voltage Reference Summary Goal: Provide stable reference voltage for the A/D converter and Filter DC Offset Input Voltage: 3.3V (nominal) Output Voltage 3.0V (+/- 1%) Part Chosen: National Semiconductor: LT1790BC

Block 2: Voltage Reference 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter Block 2: Voltage Reference Details Output Voltage: 2.99175 – 3.00825 (V) 3.0V +/- 0.275% Guaranteed over temperature range Temperature Range: -40 – 125 (oC) Temperature Coefficient: 25ppm/oC (max) Output Noise 0.1Hz<f<10Hz: 50μVP-P 10Hz<f<1kHz: 56 μVRMS

Block 2: Manufacturing Aspects 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter Block 2: Manufacturing Aspects

Block 2: Bill of Material 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter Block 2: Bill of Material NOTES All parts are machine placed SMT Contains no hazardous materials

Block 2 Functionality Testing 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter Block 2 Functionality Testing Setup a signal generator to deliver a 60kHz sine wave with an amplitude of 10mV Inject signal into the input of Block 2 Measure the voltage at the block output Node labeled OUT on schematic Gain (20LOG(Vout/Vin)) should be around 20dB Actual Gain will vary due to component tolerances Reject if gain is less than 1dB

Block 2: Reliability Data 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter Block 2: Reliability Data

Block 2: Reliability Summary 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter Block 2: Reliability Summary Failure Rate (FITs): 116.43 MTBF: 979.83 Yrs None of these parts pose a serious reliability problem for this product. No corrective action is needed

Block 2: Sustainability 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter Block 2: Sustainability Sustainability of Key Parts: No Corrective Action Required

Standard Requirements 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 2 – Filter Verification Plan Standard Requirements

Block 3 - Microcontroller 318-595 Spring 2005, Team #4 Atomic Clock Receiver Block 3 - Microcontroller Harrison Chiu

LOCATION ON BLOCK DIAGRAM 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 3 – MicroController LOCATION ON BLOCK DIAGRAM

DESCRIPTION Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 3 – MicroController DESCRIPTION A/D conversion of signal coming from filter Decodes incoming analog signal into digital data Decode signal into Time / Date Receives and output to user Sends time signal to PC

PERFORMANCE REQUIREMENTS 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 3 – MicroController PERFORMANCE REQUIREMENTS Inputs Catches analog signal in 2 min Signal process incoming data < 1min Outputs Fulfills request in 5 minutes Power Utilizes 3.3V CMOS technology

STANDARD REQUIREMENTS 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 3 – MicroController STANDARD REQUIREMENTS Physical Max Total PCB Area: 6.45cm2 Etch connections Environmental Min Operating Temp Range: 0 - 40 °C Min Operating Humidity Range: 0 - 90% Min Storage Temp Range: -10 – 50 °C Min Storage Humidity Range: 0 – 100% Max Storage Duration: 5 Years

STANDARD REQUIREMENTS 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 3 – MicroController STANDARD REQUIREMENTS Manufacturing Maximum Total Parts Count (Block):5 Maximum Unique Parts Count (Block):3 Maximum Parts & Material Cost: $10 Maximum Mfg Assembly/Test Cost: $2 Reliability Product Life, Reliability in MTBF: 10 years Safety Primary EMC Standards: EN61204-3

BLOCK DIAGRAM OF BLOCK Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 3 – MicroController BLOCK DIAGRAM OF BLOCK

Block Schematic Atomic Clock Receiver 318-595 Spring 2005, Team #4 BLOCK 3 – MicroController Block Schematic

Processor Selection A / D converter 3.3V CMOS technology 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 3 – MicroController Processor Selection A / D converter 3.3V CMOS technology 2-4K of program memory External clock Internal clock for power save mode Varying range of capable clock speeds

318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 3 – MicroController Clock Selection Desired minimal error during communications @ 9600 baud with external device If the error is greater then 0 it would present the possibility of transmission errors when communicating with an external interface Reason for selecting 3.68Mhz crystal

Clock Selection (cont.) 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 3 – MicroController Clock Selection (cont.) Calculation Desired Baud Rate = FOSC / (64 (X + 1)) Solving for X: X = ((FOSC / Desired Baud Rate)/64) – 1 X = ((3680000 / 9600) / 64) – 1 X = 4.9895833333 Calculated Baud Rate = 3680000 / (64 (4.9895833333 + 1)) = 9600 Error = (Calculated Baud Rate – Desired Baud Rate) Desired Baud Rate = (9600 – 9600) / 9600 = 0.00%

Digital Block DFM - DC Drive Analysis Table DC Drive Device Parameters 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 3 – MicroController Digital Block DFM - DC Drive Analysis Table Dig Device Output Type Input Type ech Type DC Drive Device Parameters Vil max Vih min Iil (-) Max Iih Vol Voh Iol Ioh (-) Min Vhyst Checked PIC18F2320 Std CMOS 0.66V 1.625V 2uA -2uA 0.6V 2.6V 20mA -20mA N/A 74LCX14M 1.2V 2.2V 1.5uA -1.5uA 0.8V 3.1V 24mA MAX3232C 2.0V 1uA - 1uA -5.4V 5V Component Nominal or Max Value Tolerance Around Nominal Maximum Working Voltage Composition Dielectric or Form Pkg Clock Capacitor 15pf +/- 1% 16V Ceramic SMT

Bill of Materials Atomic Clock Receiver 318-595 Spring 2005, Team #4 BLOCK 3 – MicroController Bill of Materials Totals: 186.4 mm2 $9.43

Manufacturing Processes 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 3 – MicroController Manufacturing Processes Machine Placement: PIC18F2220 Capacitor Crystal Oscillator Machine Solder:

Manufacturing Test Process 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 3 – MicroController Manufacturing Test Process Test 1 Clock Speed Verification: Action 1: Power MicroController Verify: Clock Frequency 3.68Mhz Action 2: Vary temperature 0 – 40C Verify: Clock frequency +/- 1% Test 2 Input Signal vs Output Signal Verification: Action 1: Supply a predefined simulated analog signal into A/D pin Verify: Output is the proper time output for input

Block Reliability Analysis 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 3 – MicroController Block Reliability Analysis

Block Reliability Analysis 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 3 – MicroController Block Reliability Analysis Total MTBF = 3143.4 years Dominant Reliability issues: None None of the parts pose a serious reliability issue for this product. Therefore no corrective action is required

Sustainability Aspects: Obsolescence 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 3 – MicroController Sustainability Aspects: Obsolescence   µ σ µ + 2.5σ-p µ + 3.5σ-p MicroChip PIC18F2320-I/SO Primary Attribute: Device Type (MicroController) 1990.5 9.2 8.2 17.4 Secondary Attributes: Technology (CMOS) 2010 12.5 35.95 48.45 Package style ( 28SOIC) 1995 6.5 5.95 12.45 Obsolescence Window: (5.95,12.45) No negative values so corrective actions are not required.

Block Requirement Verification 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 3 – MicroController Block Requirement Verification Block Requirement # Verification Plan Vdd is within operating range 1 Engineering Analysis Lab Test Max current consumption 2 Engineering Analysis Lab Test Processing speed 3 Lab Test Operating temperature range 4 Engineering Analysis Lab Test Max Parts Count, Max PCB Area 5 Engineering Analysis Safety Standards 6 Safety/UL Testing

Software Design Jonathan West

WWVB Radio Station Pulse Width Modulated signal sent on a 60kHz Carrier Wave Time code is 60 bits long, sent at 1 bps Each second, signal power reduced 10dB and then restored. 200ms later: 0 bit 500ms later: 1 bit 800ms later: Position Identifier

WWVB Signal Strength

Signal Decoding: Stage 1 Calculate the Power of the signal P(n) = c*P(n-1) + (1-c)x(n)2 Stop tracking signal if it becomes too weak Wait for power to stabilize Set first power level Repeat to set second power level Calculate threshold level and go to next stage

Signal Decoding: Stage 2 Find Start of Time Signal Wait for bit start: start timer Monitor timer to detect signal loss Wait for signal to rise Stop Timer and Decode Bit when Signal Rises Goal: Find 2 Position Markers Go to Stage 3

Signal Decoding: Stage 3 Decode Time Signal Input Bits using same process as in stage 2 Record bits to memory Decode Signal and update internal clock

Internal Clock: Design Timer0 Used 16 Bit Prescaler Values 2-256 Interrupt on Overflow Read/Write Capability

Internal Clock: Flow Chart

Block 5 – User Interface Harrison Chiu Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver Block 5 – User Interface Harrison Chiu

LOCATION ON BLOCK DIAGRAM 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 5 – User Interface LOCATION ON BLOCK DIAGRAM

DESCRIPTION Atomic Clock Receiver Serial interface to PC 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 5 – User Interface DESCRIPTION Serial interface to PC Visual status of sync and power Power LED Sync status ( Visual inspection of signal & Error) Controls Reset Manual Sync

PERFORMANCE REQUIREMENTS 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 5 – User Interface PERFORMANCE REQUIREMENTS Inputs Serial input complies to RS232 standards. Buttons provides response within 500ms Outputs Time output complies to RS232 standards. Physical Max Total PCB Area: 311.1mm2 Etch connections SMT packaging and miminal through hole

STANDARD REQUIREMENTS 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 5 – User Interface STANDARD REQUIREMENTS Environmental Min Operating Temp Range: 0 - 40 °C Min Operating Humidity Range: 0 - 90% Min Storage Temp Range: -10 – 50 °C Min Storage Humidity Range: 0 – 100% Max Storage Duration: 5 Years Manufacturing Maximum Total Parts Count (Block):27 Maximum Unique Parts Count (Block):5 Maximum Parts & Material Cost: $15 Maximum Mfg Assembly/Test Cost: $2

STANDARD REQUIREMENTS 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 5 – User Interface STANDARD REQUIREMENTS Reliability Allocation Product Life, Reliability in MTBF: 10 years Safety Primary EMC Standards: EN61204-3

BLOCK DIAGRAM OF BLOCK Atomic Clock Receiver 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 5 – User Interface BLOCK DIAGRAM OF BLOCK

Block Schematic Atomic Clock Receiver 318-595 Spring 2005, Team #4 BLOCK 5 – User Interface Block Schematic

LED Selection Single colored LED to control cost. Color selection 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 5 – User Interface LED Selection Single colored LED to control cost. Bi-color LED would provide space savings and easier readability Color selection Red for power Green for sync status Amber for signal acquisition error

Other De-bounce Types Hysteresis gate after switch 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 5 – User Interface Other De-bounce Types Hysteresis gate after switch Hoping that the gates input hysteresis will pull input up through threshold But will cause rail-rail switching Placing Flip-Flop after the switch hoping that the flip-flop’s feedback will cause it to change state on the first bounce. Subject to Murphy’s law and works 99% of the time Energy is enough to change state but not enough to adhere to flip-flop setup time Software Debounce

De-bounce Circuit Design 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 5 – User Interface De-bounce Circuit Design Switch open: charges capacitor Switch closed: capacitor discharges through R2 Key is to have bounce stop before the gate reaches input threshold Otherwise RC must be greater then bounce time

De-bounce Calculations 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 5 – User Interface De-bounce Calculations measured time until the gate reaches its threshold voltage is a bit longer than predicted because the switch bounce prolongs the capacitor discharge time TB=1 msec Vth=0.55VCC, R2C=1.67(10^-3) C=0.1 uF R2=16.7 kohms hysteresis gate has a threshold voltage of 0.45 to 0.55 times VCC. R2C filter causes the gate voltage to have a slow fall time. Slow rise or fall times keep the gate in its low-noise-immunity- threshold region for a long time, so you need hysteresis to pull the input out of the threshold the first time the gate switches

Digital Block DFM - DC Drive Analysis Table DC Drive Device Parameters 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 5 – User Interface Digital Block DFM - DC Drive Analysis Table Dig Device Output Type Input Type Tech Type DC Drive Device Parameters Vil max Vih min Iil (-) Max Iih Vol Voh Iol Ioh (-) Min Vhyst Checked PIC18F2320 Std CMOS 0.66V 1.625V 2uA -2uA 0.6V 2.6V 20mA -20mA N/A 74LCX14M 1.2V 2.2V 1.5uA -1.5uA 0.8V 3.1V 24mA MAX3232C 2.0V 1uA - 1uA -5.4V 5V Component Nominal or Max Value Tolerance Around Nominal Maximum Working Voltage Composition Dielectric or Form Pkg Charge Pump 0.1uF +/- 5% 25V Ceramic SMT

Bill of Materials Atomic Clock Receiver 318-595 Spring 2005, Team #4 BLOCK 5 – User Interface Bill of Materials Totals: 311.1 mm2 $24.36

Manual Manufacturing Processes 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 5 – User Interface Manual Manufacturing Processes Machine Placement: MAX3232CDR 74LCX14M DB9 Connector Resistors Capacitor Machine Solder: Manual Placement: PCB into enclosure LEDs into enclosure Momentary switches Connecting wires between PCB and enclosure Manual Solder: LED & lead wires to PCB Momentary switch & lead wires to PCB

Manufacturing Test Process 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 5 – User Interface Manufacturing Test Process Test 1 LED Visibility Verification: Action 1: Power unit up Verify: Power Led glows red and visible from 10m Action 2: Press manual sync button Verify: Sync status lights starts flashing and visible from 10m Test 2 Switch Verification: Action 1: Press white reset button while time is outputting Verify: Output stops and sync restarts Action 2: Press black manual sync button while output is idle and not syncing Verify: Unit starts syncing

Manufacturing Test Process (cont.) 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 5 – User Interface Manufacturing Test Process (cont.) Test 3 Connector Verification: Action 1: Plug a DB9 female connector to units output Verify: Female plug slides with minimal effort and is snug Action 2: Screw in connector Verify: Screws go in with no alignment problems Test 4 Output Verification: Action 1: With cable connected from test 3 connect other end to tester Verify: Output within RS232 standards Action 2: With cable connected from test 3 connect other end to tester Verify: Output is valid

Block Reliability Analysis 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 5 – User Interface Block Reliability Analysis

Block Reliability Analysis 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 5 – User Interface Block Reliability Analysis Total MTBF = 278.66 years Dominant Reliability issues: Charge pump IC has the highest failure rate None of the parts pose a real serious reliability issue for this product. Therefore no corrective action is required

Sustainability: Obsolescence 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 5 – User Interface Sustainability: Obsolescence   µ σ µ + 2.5σ-p µ + 3.5σ-p MicroChip MAX3232CDR Primary Attribute: Device Type (Charge Pump) 1990.5 9.2 8.2 17.4 Secondary Attributes: Technology (CMOS) 2010 12.5 35.95 48.45 Package style (SOIC) 1995 6.5 5.95 12.45 Process Voltage ( 3.3V) 1998.5 4.5 4.45 8.95 Obsolescence Window: (4.45,8.95) MicroChip 74LCX14M Device Type (Inverter)

Block Requirement Verification 318-595 Spring 2005, Team #4 Atomic Clock Receiver BLOCK 5 – User Interface Block Requirement Verification Block Requirement # Verification Plan RS232 Standards on Serial Output 1 Engineering Analysis & Lab Test User request satisfied by microcontroller 2 Engineering Analysis & Lab Test Visibility 3 Lab Test Operating temperature range 4 Engineering Analysis & Lab Test Max Parts Count, Max PCB Area 5 Engineering Analysis Safety Standards 6 Safety/UL Testing

Reliability, Sustainability, Post-Design Analysis Michelle Hecyk

Post Design - Legal Atomic Clock Receiver User Maintenance 318-595 Spring 2005, Team #4 Atomic Clock Receiver Post Design - Legal User Maintenance Battery replacement as needed Directed to battery manufacturer for disposal (WEEE Strategy) Product End of Life Landfill disposal recommended with removal of batteries Product Warranty Full 2 Years – return to factory for service Small number of parts makes scrapping more economical

Possible Patent Infringements 318-595 Spring 2005, Team #4 Atomic Clock Receiver Possible Patent Infringements Number: 6,532,194 Assignee: Intel Corporation (Santa Clara, CA) Risk: Relies on WWVB to obtain time Solution: Review design and confirm that infringement hasn’t occurred Number: 6,288,979 Assignee: Moneray International Ltd. (Kowloon, HK) Risk: Auto-updates internal clock using WWVB Number: 4,768,178 Assignee: Precision Standard Time, Inc. (Fremont, CA) Risk: Method of decoding and verifying WWVB Signal Review design and confirm that infringement hasn’t occurred

PRODUCT RELIABILITY KEY DATA 318-595 Spring 2005, Team #4 Atomic Clock Receiver PRODUCT RELIABILITY KEY DATA MTBF = 55.5 years Total FITs = 35398.3 350 units failed within 2 year warranty period 3.5% failure rate Warranty cost $14,000

PRODUCT RELIABILITY KEY DATA 318-595 Spring 2005, Team #4 Atomic Clock Receiver PRODUCT RELIABILITY KEY DATA Dominant parts for unreliability: 60kHz Crystal (T=8064.79):Temp close to rated Power Transformer(T=4172.42):Voltage close to rated Receiver IC(T=4613.55):Voltage close to rated Suggestions for improvement: Search for parts with better thermal properties and higher rated voltage Mission Life: 5 Years

PRODUCT RELIABILITY LIFE STRESS 318-595 Spring 2005, Team #4 Atomic Clock Receiver PRODUCT RELIABILITY LIFE STRESS Thermal Cycles Mechanical Shock Stress T (Celsius) Cycles Low High ∆T Storage -10 50 60 15 Transport -20 70 10 Standard Operation 40 43800 Worst Case 25 2190 Axis Amplitude (G Force) # of Shocks X 50 30 Y Z Vibration Axis Amplitude (Grms) Duration (hours) Freq. Range (Hz) X 5 40 10-300 Y Z 60 Values chosen similar to standard for TI calculators

PRODUCT RELIABILITY GROWTH 318-595 Spring 2005, Team #4 Atomic Clock Receiver PRODUCT RELIABILITY GROWTH HALT TEST / ACCELERATION FACTOR Stress Type Lifetime Amt Proposed Test (HALT) Accel Factor Thermal 46015 Accelerated thermal cycle 146 Shock 90 3-axis Shock simulation 584000 Vibration 140 3-axis Vibration test 3129 HALT test protocol Test 40 units with 1 failure Total Time: 315 Hours

Product Level Requirement Verification 318-595 Spring 2005, Team #4 Atomic Clock Receiver Product Level Requirement Verification Block Requirement # Verification Plan User Inputs, User Indicators and Displays, Operation Modes 1 Engineering Analysis Lab Test - Visual Inspection Electrical Interfaces, Electrical Transfer Performances 2 Lab Test - Measurements Mechanical Interfaces 3 Lab Test Manufacturing 4 Product Documentation Environmental 5 Safety 6 Lab Test – Measurements Safety/UL Testing

Obsolescence Analysis 318-595 Spring 2005, Team #4 Atomic Clock Receiver Obsolescence Analysis Summary

Obsolescence Analysis 318-595 Spring 2005, Team #4 Atomic Clock Receiver Obsolescence Analysis Use of modern technologies throughout product prevents obsolescence from being an issue for our product.

Design for Manufacturing Ned Storer

IPC Assembly Standards None of the blocks in our project require any special standards. Class 1: IPC-A-610 and IPC/EIA J-STD-001 Acceptability of Electronic Assemblies Operator Proficiency IPC-2221A, IPC-7095A, and IPC-7351 Generic standard for Printed Board Design Design and Assembly Process Implementation for BGA’s Generic requirements for Surface Mount design and Land Pattern standard

Circuit Functionality Tests Apply power to circuit and verify 3.3Vdc is at all needed points Verify antenna is receiving a signal Verify the microcontroller program is working Verify all user interfaces Simulate RS232 communication protocol

DFM – Assembly Process Step 1: Step 2: Step 3: Organize and components for soldering Step 2: Solder components on PCB Mount antenna onto PCB Step 3: Program Microcontroller Perform functionality test

DFM – Assembly Process Step 4: Step 5: Step 6: Mount buttons and DB9 connector on enclosure Solder wires from PCB to switches and DB9 connector Mount PCB in enclosure Step 5: Seal Case Step 6: Place product in packaging and prepare for shipment

PCB Layout Only one (1) PCB is required for the Atomic Clock Receiver. The PCB will be a two-sided board with a silkscreen on the component side and a solder mask on both sides. A ground plane will be placed on the non-component side. The size of the PCB is 2.5” X 3.8”

Mass Production BOM

Mass Production BOM Continued

Label Designs for Product Exterior

Label Designs for Product Exterior Electric Shock Hazard

Assembly Flowchart

PCB Cost Cost for PCB Tooling Setup = $223.00 Cost for each PCB = $4.92

EE 595 – Atomic Clock Receiver The Prototype Ned Storer

Integration of Prototype The prototype integration was chosen to be a simple PCB. A breadboard was not chosen due the high levels of noise present in a breadboard. The ground plane on the PCB will highly reduce noise. The component technology chosen for the prototype was Surface Mount whenever it was possible.

Prototype Cost and PCB Area Total Cost for Prototype Materials = $276.17 --------------------------------------------------------------- Cost for prototype parts was higher than needed due low quantities and due to minimum purchase quantities Cost for prototype components = $217.17

Prototype Cost and PCB Area To reduce the cost of the prototype PCBs, a silkscreen was not used. To help further reduce costs, solder masks were also not used on the prototype PCB. Area of PCB -> 3.8” X 2.5” = 9.5” Cost for prototype PCB’s = $59.00

Prototype BOM

Prototype BOM Continue

Prototype Schematic

PCB Layout

Picture of Prototype

Acknowledgements Pentair Water Treatment Chris Merkl Jeff Kautzer Mike Lindfors Chris Merkl Jeff Kautzer

Prototype Demonstration Jonathan West

Functions Demonstrated Internal Clock Yellow LED Blink every second Full time stored in memory A/D Conversion Simulated signal provided by 2nd microcontroller Status of ADRESH Register shown on Green LED

Questions?

Appendices

PRODUCT RELIABILITY GROWTH 318-595 Spring 2005, Team #4 Atomic Clock Receiver PRODUCT RELIABILITY GROWTH HALT test protocol Test 40 units with 1 failure Thermal Test units using thermal cycling from 10 to 25°C for 300 cycles with 1 failure 60 minute interval for each test Total test time = 300 hours Acceleration factor: 43800hr/300hr=146

PRODUCT RELIABILITY GROWTH 318-595 Spring 2005, Team #4 Atomic Clock Receiver PRODUCT RELIABILITY GROWTH HALT test protocol Shock Test units using shock force of 50G’s on X, Y, Z axes 30 times each with 1 failure 3 second interval for each test Total test time = .075 hr Acceleration factor: 43800hr/.075hr=584000

PRODUCT RELIABILITY GROWTH 318-595 Spring 2005, Team #4 Atomic Clock Receiver PRODUCT RELIABILITY GROWTH HALT test protocol Vibration Test units on X and Y axes at 5Grms for 4 hours each and Z axis at 5Grms for 6 hours with 1 failure Total test time = 14 hours Acceleration factor: 43800hr/14hr=3129

Project Level Gantt Chart 318-595 Spring 2005, Team #4 Atomic Clock Receiver Project Level Gantt Chart

Internal Serial Connector

Internal Interrupt Connectors

Special Safety Features Considerations were made regarding over-power protection for Block but are not currently being pursued.

Digital Signal Interface Requirements Effectiveness Not Applicable Digital Signal Interface Requirements None

Design for Mass Production 318-595 Spring 2005, Team #4 Atomic Clock Receiver Design for Mass Production IPC or Other Assembly Workmanship Standards for ALL PCBs All Levels of Assembly and Test clearly depicted, Mfg Process Diagram & plans Number and Sizes of PCBs Clearly defined Composite Mass Production Parts List and Structure All Internal/External Cables & Connectors Specified in Master Parts List Label Designs for Exterior of Product (warnings, functions, etc) Assembly flow diagram for PCBs and other Assembly Levels incl Tests Key interim or final tests (what parameters need to be tested, how) Mfg Setup Costs: Tooling, PCB test fixtures, Fab Tooling