E. Hazen - Back-End Report AMC13 Status Report 2012-12-11 E. Hazen - Back-End Report

E. Hazen - Back-End Report AMC13 Status Reminder Version 1 (5Gb/s links, Virtex-6 chip) 15 modules built, all but 3 distributed to colleagues 1 at P5 participating for Slice test Version 2 (10Gb/s links, Kintex-7 chip) Design ready to send out, expect to send in next days Prototypes ready in mid-January 2 pcs initial for lab testing 15 pcs total to produce (aim: yield > 12) 2012-12-11 E. Hazen - Back-End Report

E. Hazen - Back-End Report AMC13 Rev 2 Changes Virtex 6 to Kintex 7 for 10G link support Two-way GbE switch removed, GbE to Spartan chip only (Never used Virtex GbE option) SDRAM size increased from 128MB to 512MB speed to 800MHz DDR (1600MT/s * 16 bits) Clock source changes: Rev 1 used 2x Si570 programmable XO Rev 2 uses Si5338B Quad programmable clock generator TTC Recovered clock to clock-capable input on Kintex 7 Changes to T1-T2 board connector pinout Maintain plug compatibility with existing connector Add 1 pin for additional 12V to be routed to T3 (plus additional GND) There are two diff pairs unused (GPIO pairs) unused for CLK, TTC 2012-12-11 E. Hazen - Back-End Report

E. Hazen - Back-End Report Slice Test MicroTCA Crate installed with AMC13 and mCTR2 Firmware and software in place Full DAQ firmware for mCTR2c and AMC13 Full xDAQ control and readout software Runs taken at P5! Bunch structure seen LED and laser runs taken and verified Parasitic collider run taken and being analyzed 25 events captured by HLT via normal CDAQ and saved (save 1/2^20 L1A) 28 events captured by uTCA monitor buffer EvN, OrN and BcN match (there is a BcN offset...) Working on matching of QIE data... seems to be 3-sample offset Data format very close to VME, so CMSSW analysis chain should work without much trouble on uTCA data uTCA crate at P5 with AMC13 and 6 mCTR2 2012-12-11 E. Hazen - Back-End Report

E. Hazen - Back-End Report Reserve Slides 2012-12-11 E. Hazen - Back-End Report

E. Hazen - Back-End Report TTC / TTS Tester VME (or benchtop) module TTS fiber-to-RJ45 translator TTC system simulator 10 pieces at assembly house, overdue! Firmware underway; basic version running, fancy version with IPBus control in development 2012-12-11 E. Hazen - Back-End Report

E. Hazen - Back-End Report Slice Test 2012-12-11 E. Hazen - Back-End Report

TTC/TTS Tester Diagram 2012-12-11 E. Hazen - Back-End Report

E. Hazen - Back-End Report AMC13 Module – Rev 2 CLK F/O 40.xx CLK To AMCs CDS TTC in TTS out Kintex 7 SFP IO IO DAQ 10 Gb/s SFP+ GTX GTX GTX GTX Fabric A (DAQ) 12 ports 5.0 Gb/s GTX GTX DAQ 10 Gb/s SFP+ GTX GTX GTX GTX GTX Spare 10 G b/s SFP+ (2) 128Mx16 DDR3 GTX 1600MT/s (6.4 GB/s) Spartan 6 GTP IO Fabric B 80 Mb/s (TTC) DC LVDS GbE GTP MCH1 MMC uC IPMI Front Panel via T3 JTAG LEDs SPI Flash (4x GPIO) 2012-12-11 E. Hazen - Back-End Report

E. Hazen - Back-End Report SDRAM Update Rev 1: (1) MT41J64M16LA 64M x 16 DDR3 Tested at 1600 MT/s (800 MHz) Rev 2: (2) MT41J128M16JT-107 128M x 16 DDR3 Speed rated to 1866 MT/s (933 MHz) Plan to operate at 1600 MT/s (800 MHz) This part promised long-term availability by Micron factory rep 2012-12-11 E. Hazen - Back-End Report

E. Hazen - Back-End Report New clock source 2012-12-11 E. Hazen - Back-End Report

E. Hazen - Back-End Report T1-T2 connectors MMC T2 → T1 SPI Bus Switch, LEDs Propose to add 1-2 pins PWR12V Connector can expand this way only 2.5Gb/s T1 ↔ T2 link GbE to T2 T1 → T2 TTC Data 40MHz clk Spare GPIOs (4) JTAG / Config JTAG / Config 2012-12-11 E. Hazen - Back-End Report

E. Hazen - Back-End Report Clocks: Rev 1 2012-12-11 E. Hazen - Back-End Report

E. Hazen - Back-End Report Clocks: Rev 2 2012-12-11 E. Hazen - Back-End Report

E. Hazen - Back-End Report AMC13 Rev 1 Hardware Tongue 3 PCB (optional, for initial programming) (4) SFP+ Sites 1 for TTC (160Mb) 3 for DAQ/etc 6.2Gb Atmel AVR-32 uC MMC Functions Micro USB MMC serial console Tongue 2 PCB Tongue 1 PCB Spartan 6 FPGA Fabric B TTC distribution Firmware management interface to MMC Virtex-6 LX130T FPGA DAQ Functions, buffering 6Gb links to backplane, SFP JTAG Headers MMC programming FPGA programming 2012-12-11 E. Hazen - Back-End Report