Investigation of an abnormal pattern of leakage currents in silicon microstrip detectors I. Rashevskaya on behalf of the Slim5 Collaboration, Trieste Group Abstract Some batches of microstrip detectors fabricated by FBK-irst showed an odd and peculiar pattern of the strip leakage currents: the first and last few strips of the detector had low leakage, whereas all the strips in between showed very high current (3-5 orders of magnitude higher). Due to the peculiar shape of the strip current plot, the phenomenon has been called “panettone effect”. This characteristic was common to all detectors within the affected batches. A detailed study of detectors and test structures made with a few variations of the fabrication process led us to conclude that the high strip currents were due to stress induced in the silicon by the combination of LPCVD-deposited layers of TEOS oxide and nitride. The strips close to detector ends had low current because there the stress was locally relaxed by the presence along the bias ring of a continuous contact opening through the dielectric layers. In accordance with this interpretation, some modifications have been introduced in the fabrication process, resulting in detectors with low leakage current for all strips, showing no particular distribution pattern. Possible causes of the effect Strip current scan of an “S2” detector Example of the current distribution on a 128-strip detector. The current of the first and the last few strips is low, whereas all the strips in between have very high current (3-5 orders of magnitude higher). This peculiar phenomenon, common to ALL six different detectors in EACH wafer of the batch, has been called “Panettone effect”. The “panettone effect” has been observed on wafers with and without gettering. Although the current of test diodes and of the first strips is two orders of magnitude lower on the gettered wafers, the central strips have about the same current. Therefore, bulk generation is not likely to be the source of the high current of central strips. The strip current grows moderately with bias voltage, but the “panettone effect” is already present at low bias voltages, and there is no change when depletion voltage is exceeded. Then one can conclude that the effect cannot be connected to defects on the back side. In order to verify a possible connection of the problem to the design of the SLIM detectors, single side detectors from another batch (denoted as “RadHard”), having the layout of Babar Model 2, have been tested. All show the “panettone effect”. The same has been observed on other detectors fabricated by FBK-irst on various types of substrates (epitaxial, float zone, p-typee) with various designs. Four wafers without passivation (batch SLIMbis) have shown the same “panettone effect” of lot SLIM1. Therefore the passivation cannot be responsible for the problem. Panettone effect Possible causes First 20 strips Last 20 strips 3 5 The possible causes of the effect S1 S2 4 6 Role of surface generation current Current distribution on a “CAP” test structure Although Gated-Diodes included in test structures showed low surface currents, the characteristics of the currents measured on strip detectors led us to suspect that surface generation played a major role there. In order to verify this hypothesis, the condition of the Si-SiO2 interface in the interstrip gaps of a sensor has been controlled with a gate, obtained by extending the metal strips with a layer of conductive paint. Silver paint The total detector current (I_back) shows the V_gate dependence typical of a Gated Diode (plot (a)). In accumulation and depletion, the current measured on a strip (I_strip) follows exactly the same shape of I_total, with a scale factor ≈ 119 ≈ number of high-current strips (see plot (b)). Once surface inversion channels start to form, the strip current grows much higher, because it collects the charge from many other strips. Eventually, the strip and backside currents decrease to low values when all the surface is inverted, suppressing the surface generation. The high current measured on strip detectors is quantitatively compatible with this surface-generated current in the interstrip gaps. It must be concluded that in the gaps between the strips of the detectors the interface has much worse characteristics than in the gated diodes. (a) Additional measurement The fact that the first and last strips show normal current suggests that the proximity to some feature of the detector edge could be a factor influencing the current. Two candidates are the Bias Ring or the n-type implant running all along the cut lane. In order to distinguish between these possibilities, we measured the currents of a test structure, designed for interstrip capacitance measurements, which has four groups of 13 strips, separated by a common Bias Ring. The peculiar pattern of strip currents is reproduced within each group of strips. The number of low-current strips at the ends is the same as in large sensors having the same strip pitch. Confronting detectors with different pitches, we see that low-current strips extend up to about the same distance from the bias ring. This suggest that proximity to the bias ring, rather than to the n-type edge implant, is what makes low-current possible. (b) Proposed explanation for the origin of the effect Further support of the interpretation missing along a fraction of the length of a few strips. This caused the contact etch between metal and poly to penetrate down to the implanted strip, thus cutting through all dielectric layers. According to our interpretation, this locally releases the stress, yielding lower current for the strips with interrupted polysilicon and a few of their neighbors. By comparing the technologies of different detector lots fabricated by FBK-irst, we observe that the peculiar 'Panettone Effect' is correlated with the combined presence of two LPCVD-deposited dielectric layers: silicon nitride and TEOS oxide. (NO POLY) In a few cases, a number of strips in the high-current central region of the sensor showed a reduced current. Visual inspection revealed that the polysilicon layer was We can hypothesize that this combination produces a high level of stress, which induces defects at the silicon/oxide interface, leading to a high rate of surface generation. These dielectric layers are interrupted in the contact areas between metal and (implanted) silicon. This locally releases the stress in a region around the contact. Since the Bias Rings of the detectors (as well as the Guard Rings of the test structures) have a continuous contact opening along their length, the local release of the stress can explain the fact that the strips within a certain distance from the Rings have low leakage current. The fact that gated diode test structures show low surface generation currents is due to their small size: all regions of the structure are within a short distance from the surrounding Guard Ring. It should be noted that this picture assumes the interface defect generation due to stress to be a reversible process: defects are removed once the stress is released by opening the contact. Making use of a modified technology excluding the TEOS oxide, a batch of striplet detectors has been fabricated. They showed no “panettone effect”, and have been successfully employed in the SLIM5 beam test at CERN in September 2008. Related Presentation on the 2009 Pisa Meeting Lorenzo Vitale on behalf of SLIM5 collaboration, SLIM5 Beam Test Results for Thin Striplet Detector and Fast Readout Beam Telescope Mauro Villa  on behalf of SLIM5 collaboration, Beam-Test Results of 4k pixel CMOS MAPS and High Resistivity Striplet Detectors Equipped with Digital Sparsified Readout