Microfabrication Home exercise 1

Slides:



Advertisements
Similar presentations
FABRICATION PROCESSES
Advertisements

CMOS Fabrication EMT 251.
Wally Dream Job.
OXIDATION- Overview  Process Types  Details of Thermal Oxidation  Models  Relevant Issues.
Fabrication of p-n junction in Si Silicon wafer [1-0-0] Type: N Dopant: P Resistivity: Ω-cm Thickness: µm.
Design and Implementation of VLSI Systems (EN1600) lecture04 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Sedra/Prentice.
Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.
Device Fabrication Example
CMOS Process Integration ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May March 25, 2004.
Katedra Experimentálnej Fyziky Bipolar technology - the size of bipolar transistors must be reduced to meet the high-density requirement Figure illustrates.
ES 176/276 – Section # 2 – 09/19/2011 Brief Overview from Section #1 MEMS = MicroElectroMechanical Systems Micron-scale devices which transduce an environmental.
CS/EE 6710 CMOS Processing. N-type Transistor + - i electrons Vds +Vgs S G D.
Surface MEMS 2014 Part 1
INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #2. Chip Fabrication  Silicon Ingots  Wafers  Chip Fabrication Steps (FEOL, BEOL)  Processing Categories 
Outline Introduction CMOS devices CMOS technology
Gas-to Solid Processing surface Heat Treating Carburizing is a surface heat treating process in which the carbon content of the surface of.
SEMINAR ON IC FABRICATION MD.ASLAM ADM NO:05-125,ETC/2008.
Semiconductor Manufacturing Technology Michael Quirk & Julian Serda © October 2001 by Prentice Hall Chapter 9 IC Fabrication Process Overview.
SEMINAR PRESENTATION ON IC FABRICATION PROCESS
Introduction to CMOS VLSI Design CMOS Fabrication and Layout Harris, 2004 Updated by Li Chen, 2010.
Elemental silicon is melted and grown into a single crystal ingot Single crystal ingot being grown Completed silicon ingot.
Lecture 24a, Slide 1EECS40, Fall 2004Prof. White Lecture #24a OUTLINE Device isolation methods Electrical contacts to Si Mask layout conventions Process.
INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #3. Diffusion  Introduction  Diffusion Process  Diffusion Mechanisms  Why Diffusion?  Diffusion Technology.
Introduction to Wafer fabrication Process
INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #4. Ion Implantation  Introduction  Ion Implantation Process  Advantages Compared to Diffusion  Disadvantages.
Presentation Outline February 25 th 20112Microfabrication Design Challenge 2011.
Silicon detector processing and technology: Part II
Thermal doping review example This presentation is partially animated. Only use the control panel at the bottom of screen to review what you have seen.
IC Processing. Initial Steps: Forming an active region Si 3 N 4 is etched away using an F-plasma: Si3dN4 + 12F → 3SiF 4 + 2N 2 Or removed in hot.
IC Fabrication/Process
CORPORATE INSTITUTE OF SCIENCE & TECHNOLOGY, BHOPAL DEPARTMENT OF ELECTRONICS & COMMUNICATIONS NMOS FABRICATION PROCESS - PROF. RAKESH K. JHA.
©2008 R. Gupta, UCSD COSMOS Summer 2008 Chips and Chip Making Rajesh K. Gupta Computer Science and Engineering University of California, San Diego.
Midterm Exam Question (Thermal doping review) This presentation is partially animated. Only use the control panel at the bottom of screen to review what.
Microfabrication CHEM-E5115
CMOS VLSI Fabrication.
Side ViewTop View Beginning from a silicon wafer.
(Chapters 29 & 30; good to refresh 20 & 21, too)
Microfabrication Home exercise #3 Return by Feb 21st, 22 o’clock
KUKUM – SHRDC INSEP Training Program 2006 School of Microelectronic Engineering Lecture V Thermal Processes.
Introduction to microfabrication, chapter 1 Figures from: Franssila: Introduction to Microfabrication unless indicated otherwise.
CMOS Fabrication EMT 251.
CMOS VLSI Design Lecture 2: Fabrication & Layout
Scaling
Process integration 2: double sided processing, design rules, measurements
IC Manufactured Done by: Engineer Ahmad Haitham.
Home 2 Return by January 29th, o’clock Into Return box 2 in MyCourses.
Basic Planar Processes
Process integration 1: cleaning, sheet resistance and resistors, thermal budget, front end
CMOS Fabrication CMOS transistors are fabricated on silicon wafer
Fabrication Process terms
Simplified process flow for bonding interface characterization
Microfabrication Home 3 exercise Return by Feb 5th, 22 o’clock
Microfabrication CHEM-E5115 sami. fi victor
Manufacturing Process I
EMT362: Microelectronic Fabrication
Microelectronic Fabrication
Fab. Example: Piezoelectric Force Sensor (1)
VLSI System Design LEC3.1 CMOS FABRICATION REVIEW
Silicon Wafer cm (5’’- 8’’) mm
Solid State Devices Fall 2011
Lecture #25 OUTLINE Device isolation methods Electrical contacts to Si
Process flow part 2 Develop a basic-level process flow for creating a simple MEMS device State and explain the principles involved in attaining good mask.
Manufacturing Process I
Chapter 1.
Wally Dream Job.
Manufacturing Process I
Elemental silicon is melted and grown into a single crystal ingot
CSE 87 Fall 2007 Chips and Chip Making
Basic Planar Process 1. Silicon wafer (substrate) preparation
Presentation transcript:

Microfabrication Home exercise 1 Deadline for returns 22th January, 2017, 10 pm into MyCourses return box 1.

Q1: Silicon doping level a) Consider an Olympic swimming pool filled with golf balls (representing silicon atoms) and one squash ball (representing boron dopant). If a silicon wafer had similar doping concentration, what would be its resistivity? Hint: Use Fig. 4.1 for doping vs. resistivity conversion. b) Typical oxygen concentration in silicon is 15 ppma (parts per million atoms). If cricket balls represent oxygen atoms, how many of them should be found in our swimming pool ? Note: this is an order of magnitude exercise: use single digit accuracy only, e.g. 2 cm radius and give doping level as e.g. 8*1019 cm-3.

Q2: Thermal oxidation a) If 250 minute wet oxidation results in 1 µm thick oxide, how long will it take to grow 5 µm oxide under same conditions? b) How long will it take to grow 200 nm thick oxide? Hint: Use the parabolic assumption, figure 13.3.

Q3: Ion implantation a) 150 mm diameter wafers are implanted with 100 µA current of B+ ions. How long does it take if the dose is 1014 cm-2 ? b) If CMOS source/drain areas are implanted with 1015 cm-2 dose and the depth is 200 nm, what is the doping concentration in those areas ?

Q4: Oxides Explain the main similarities and differences between thermal oxide and CVD oxide.

Q5: FLEEESLESLEES… Spot exercise 1 revisited: Provide a letter sequence fabrication process for them ! L = Lithography E = Etch F = Film deposition S = Strip resist

Q6: Thermal oxidation Draw where 200 nm thick thermal oxide will grow in the structure shown below. Detail drawing needed; no points for hasty sketches. For once, this drawing is to scale: the trench width is 1 µm, poly is 500 nm thick, and so on. (However, n+ substrate is 500 µm thick). Hint: take a photo and copy-paste into your document.