Summary of discussion in 3D Design Group during ITk Week

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Presentation transcript:

Summary of discussion in 3D Design Group during ITk Week Gian-Franco Dalla Betta1, Giovanni Darbo2 1University of Trento and TIFPA INFN, Trento, Italy 2INFN Genova, Italy Layout options for next 3D batch Thickness issues

FEI4 compatible test pixels 50 x 50 2x50 + 2x450 2x50 + 2x450L 4x50 + grid 450 mm 450 fF 250 fF 250 fF 50 mm 450 mm

Other issues SENSOR LAYOUT SENSOR THICKNESS Add FEI3 pixel designs Slim edge: 3D guard ring vs ohmic fence – not be too aggressive in the “tile floorplan” – test very slim separately? Common “tile floorplan” with other 3D foundries (CNM…): same type of structure in corresponding tile regions – simpler for test beam and analysis. Critical points for 25x100 pixels – have these pixels in separate tiles (may kill yield) Bump pad size Capacitance SENSOR THICKNESS For 3D sensors “very thin” is not convenient Is there an optimum value ? (signal efficiency/charge vs noise) Only a small fraction of pixels will exploit the thickness for signal, for all the others it is the pixel size that matters (for 200µm thick sensor only tracks between 75º to 90º could fully traverse a 50µm x 50µm pixel) Try 1E version ?