SEQUENTIAL LOGIC

Sequential Logic

Positive Feedback: Bi-Stability

Meta-Stability Gain should be larger than 1 in the transition region

SR-Flip Flop S R Q 1 Q Q S R Q Q S Q 1 1 Q Q R Q 1 1 1 1 1 1

JK- Flip Flop

Other Flip-Flops

Race Problem

Master-Slave Flip-Flop

Propagation Delay Based Edge-Triggered

Edge Triggered Flip-Flop

Flip-Flop: Timing Definitions

Maximum Clock Frequency

CMOS Clocked SR- FlipFlop

Flip-Flop: Transistor Sizing

6 Transistor CMOS SR-Flip Flop

Charge-Based Storage

Master-Slave Flip-Flop

2 phase non-overlapping clocks

2-phase dynamic flip-flop

Flip-flop insensitive to clock overlap

C2MOS avoids Race Conditions

Pipelining

Pipelined Logic using C2MOS

Example

NORA CMOS Modules

Doubled C2MOS Latches

TSPC - True Single Phase Clock Logic

Master-Slave Flip-flops

Schmitt Trigger VTC with hysteresis Restores signal slopes

Noise Suppression using Schmitt Trigger

CMOS Schmitt Trigger Moves switching threshold of first inverter

Schmitt Trigger Simulated VTC

CMOS Schmitt Trigger (2)

Multivibrator Circuits

Transition-Triggered Monostable

Monostable Trigger (RC-based)

Astable Multivibrators (Oscillators)

Voltage Controller Oscillator (VCO)

Relaxation Oscillator

Arithmetic Building Blocks

A Generic Digital Processor

Building Blocks for Digital Architectures Arithmetic unit - Bit-sliced datapath ( adder , multiplier, shifter, comparator, etc.) Memory - RAM, ROM, Buffers, Shift registers Control - Finite state machine (PLA, random logic.) - Counters Interconnect - Switches - Arbiters - Bus

Bit-Sliced Design

Full-Adder

The Binary Adder

Express Sum and Carry as a function of P, G, D

The Ripple-Carry Adder

Complimentary Static CMOS Full Adder

Inversion Property

Minimize Critical Path by Reducing Inverting Stages

The better structure: the Mirror Adder

The Mirror Adder The NMOS and PMOS chains are completely symmetrical. This guarantees identical rising and falling transitions if the NMOS and PMOS devices are properly sized. A maximum of two series transistors can be observed in the carry- generation circuitry. When laying out the cell, the most critical issue is the minimization of the capacitance at node Co. The reduction of the diffusion capacitances is particularly important. The capacitance at node Co is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell . The transistors connected to Ci are placed closest to the output. Only the transistors in the carry stage have to be optimized for optimal speed. All transistors in the sum stage can be minimal size.

Quasi-Clocked Adder

NMOS-Only Pass Transistor Logic

NP-CMOS Adder

NP-CMOS Adder C o1 S 1 A 1 B 1 S A B C i0

Manchester Carry Chain

Sizing Manchester Carry Chain

Carry-Bypass Adder

Manchester-Carry Implementation

Carry-Bypass Adder (cont.)

Carry Ripple versus Carry Bypass

Carry-Select Adder

Carry Select Adder: Critical Path

Linear Carry Select

Square Root Carry Select

Adder Delays - Comparison

LookAhead - Basic Idea

Look-Ahead: Topology

Logarithmic Look-Ahead Adder

Brent-Kung Adder

The Binary Multiplication

The Binary Multiplication

The Array Multiplier

The MxN Array Multiplier — Critical Path

Carry-Save Multiplier

Adder Cells in Array Multiplier

Multiplier Floorplan

Wallace-Tree Multiplier

Multipliers —Summary

The Binary Shifter

The Barrel Shifter Area Dominated by Wiring

4x4 barrel shifter Widthbarrel ~ 2 pm M

Logarithmic Shifter

0-7 bit Logarithmic Shifter 3 Out3 A 2 Out2 A 1 Out1 A Out0

Design as a Trade-Off

Layout Strategies for Bit-Sliced Datapaths

Layout of Bit-sliced Datapaths

Layout of Bit-sliced Datapaths

COPING WITH INTERCONNECT

Impact of Interconnect Parasitics

Nature of Interconnect

INTERCONNECT

Capacitance: The Parallel Plate Model

Typical Wiring Capacitance Values

Fringing Capacitance

Fringing Capacitance: Values

How to counter Clock Skew?

Interwire Capacitance

Interwire Capacitance

Impact of Interwire Capacitance

Capacitance Crosstalk

How to Battle Capacitive Crosstalk

Driving Large Capacitances

Using Cascaded Buffers

tp in function of u and x

Impact of Cascading Buffers

Output Driver Design

How to Design Large Transistors

Bonding Pad Design Bonding Pad GND 100 mm Out VDD Out In GND

Reducing the swing Also results in reduction in power dissipation Reducing the swing potentially yields linear reduction in delay Also results in reduction in power dissipation Requires use of “sense amplifier” to restore signal level

Charge Redistribution Amplifier

Precharged Bus

Tristate Buffers

Using Bipolar Versus MOS But: Bipolar does not scale well with voltage!

Bipolar Versus MOS (cont.)

INTERCONNECT

Wire Resistance

Interconnect Resistance

Dealing with Resistance

Polycide Gate Mosfet

Modern Interconnect

RI Introduced Noise

Power and Ground Distribution

Electromigration (1)

Electromigration (2)

RC-Delay

RC-Models

Reducing RC-delay Repeater

The Ellmore Delay

Penfield-Rubinstein-Horowitz

INTERCONNECT

Inductive Effects in Integrated Circuits

L di/dt

L di/dt: Simulation

Choosing the Right Pin

Decoupling Capacitors

The Transmission Line

Lossless Transmission Line - Parameters

Wave Propagation Speed

Wave Reflection for Different Terminations

Transmission Line Response (RL= )

Lattice Diagram

ECL Gate Line Response

Output Buffer Model

Output Buffer - Response

When to Consider Transmission Line Effects?

Packaging

Bonding Techniques

Tape-Automated Bonding (TAB)

Flip-Chip Bonding

Package-to-Board Interconnect

Package Types

Package Parameters

Multi-Chip Modules

ISSUES IN TIMING

The Clock Skew Problem

Delay of Clock Wire

Constraints on Skew

Clock Constraints in Edge-Triggered Logic

Positive and Negative Skew

Clock Skew in Master-Slave Two Phase Design

Clock Skew in 2-phase design

How to counter Clock Skew?

Clock Distribution

Clock Network with Distributed Buffering

Example: DEC Alpha 21164

Clock Skew in Alpha Processor

Self-timed and asynchronous design

Self-timed pipelined datapath

Completion Signal Generation

Completion Signal Generation

Completion Signal in DCVSL

Self-timed Adder

Hand-shaking Protocol

Event Logic — The Muller C-element

2-phase Handshake Protocol

Example: Self-timed FIFO

4-phase Handshake Protocol (or RTZ)

4-phase Handshake Protocol -Implementation

Asynchronous-Synchronous Interface

A Simple Synchronizer

Synchronizer: Output Trajectories

Simulated Trajectory versus One Pole Model

Mean Time to Failure

Example

Cascaded Synchronizers Reduce MTF

Arbiters

Synchronization at System Level

Skew of Local Clocks vs Reference

Phase-Locked Loop Based Clock Generator

Ring Oscillator

Example of PLL-generated clock

Design Methodologies

The Design Problem Source: sematech97 A growing gap between design complexity and design productivity

Design Methodology Design process traverses iteratively between three abstractions: behavior, structure, and geometry More and more automation for each of these steps

Design Analysis and Verification Accounts for largest fraction of design time More efficient when done at higher levels of abstraction - selection of correct analysis level can account for multiple orders of magnitude in verification time Two major approaches: Simulation Verification

Digital Data treated as Analog Signal Circuit Simulation Both Time and Data treated as Analog Quantities Also complicated by presence of non-linear elements (relaxed in timing simulation)

Representing Data as Discrete Entity Discretizing the data using switching threshold The linear switch model of the inverter

Circuit versus Switch-Level Simulation

Structural Description of Accumulator Design defined as composition of register and full-adder cells (“netlist”) Data represented as {0,1,Z} Time discretized and progresses with unit steps Description language: VHDL Other options: schematics, Verilog

Behavioral Description of Accumulator Design described as set of input-output relations, regardless of chosen implementation Data described at higher abstraction level (“integer”)

Behavioral simulation of accumulator Discrete time Integer data (Synopsys Waves display tool)

Timing Verification Enumerates and rank orders critical timing paths Critical path Enumerates and rank orders critical timing paths No simulation needed! (Synopsys-Epic Pathmill)

Issues in Timing Verification False Timing Paths

Implementation Methodologies

Custom Design – Layout Editor Magic Layout Editor (UC Berkeley)

Symbolic Layout Dimensionless layout entities Only topology is important Final layout generated by “compaction” program Stick diagram of inverter

Cell-based Design (or standard cells) Routing channel requirements are reduced by presence of more interconnect layers

Standard Cell — Example [Brodersen92]

Standard Cell - Example 3-input NAND cell (from Mississippi State Library) characterized for fanout of 4 and for three different technologies

Automatic Cell Generation Random-logic layout generated by CLEO cell compiler (Digital)

Module Generators — Compiled Datapath

Macrocell Design Methodology Floorplan: Defines overall topology of design, relative placement of modules, and global routes of busses, supplies, and clocks Interconnect Bus Routing Channel

Macrocell-Based Design Example SRAM SRAM Data paths Routing Channel Standard cells Video-encoder chip [Brodersen92]

Gate Array — Sea-of-gates Uncommited Cell Committed Cell (4-input NOR)

Sea-of-gate Primitive Cells Using oxide-isolation Using gate-isolation

Sea-of-gates Random Logic Memory Subsystem LSI Logic LEA300K (0.6 mm CMOS)

Prewired Arrays Categories of prewired arrays (or field-programmable devices): Fuse-based (program-once) Non-volatile EPROM based RAM based

Programmable Logic Devices PAL PLA PROM

EPLD Block Diagram Primary inputs Macrocell Courtesy Altera Corp.

Field-Programmable Gate Arrays Fuse-based Standard-cell like floorplan

Interconnect Programming interconnect using anti-fuses

Field-Programmable Gate Arrays RAM-based

RAM-based FPGA Basic Cell (CLB) Courtesy of Xilinx

RAM-based FPGA Xilinx XC4025

Taxonomy of Synthesis Tasks

Design for Test

Validation and Test of Manufactured Circuits Goals of Design-for-Test (DFT) Make testing of manufactured part swift and comprehensive DFT Mantra Provide controllability and observability Components of DFT strategy Provide circuitry to enable test Provide test patterns that guarantee reasonable coverage

Test Classification Diagnostic test “go/no go” or production test used in chip/board debugging defect localization “go/no go” or production test Used in chip production Parametric test x e [v,i] versus x e [0,1] check parameters such as NM, Vt, tp, T

Design for Testability Exhaustive test is impossible or unpractical

Problem: Controllability/Observability Combinational Circuits: controllable and observable - relatively easy to determine test patterns Sequential Circuits: State! Turn into combinational circuits or use self-test Memory: requires complex patterns Use self-test

Test Approaches Ad-hoc testing Scan-based Test Self-Test Problem is getting harder increasing complexity and heterogeneous combination of modules in system-on-a-chip. Advanced packaging and assembly techniques extend problem to the board level

Generating and Validating Test-Vectors Automatic test-pattern generation (ATPG) for given fault, determine excitation vector (called test vector) that will propagate error to primary (observable) output majority of available tools: combinational networks only sequential ATPG available from academic research Fault simulation determines test coverage of proposed test-vector set simulates correct network in parallel with faulty networks Both require adequate models of faults in CMOS integrated circuits

Fault Models a, g : x1 sa1 b : x1 sa0 or x2 sa0 g : Z sa1 Most Popular - “Stuck - at” model Covers almost all (other) occurring faults, such as opens and shorts. a, g : x1 sa1 b : x1 sa0 or x2 sa0 g : Z sa1

Problem with stuck-at model: CMOS open fault Sequential effect Needs two vectors to ensure detection! Other options: use stuck-open or stuck-short models This requires fault-simulation and analysis at the switch or transistor level - Very expensive!

Problem with stuck-at model: CMOS short fault Causes short circuit between Vdd and GND for A=C=0, B=1 Possible approach: Supply Current Measurement (IDDQ) but: not applicable for gigascale integration

Path Sensitization Goals: Determine input pattern that makes a fault controllable (triggers the fault, and makes its impact visible at the output nodes) sa0 1 Fault enabling 1 1 1 1 1 Fault propagation Techniques Used: D-algorithm, Podem

Ad-hoc Test Inserting multiplexer improves testability

Scan-based Test

Polarity-Hold SRL (Shift-Register Latch) Introduced at IBM and set as company policy

Scan-Path Register

Scan-based Test —Operation

Scan-Path Testing Partial-Scan can be more effective for pipelined datapaths

Boundary Scan (JTAG) Board testing becomes as problematic as chip testing

Self-test Rapidly becoming more important with increasing chip-complexity and larger modules

Linear-Feedback Shift Register (LFSR) Pseudo-Random Pattern Generator

Signature Analysis Counts transitions on single-bit stream  Compression in time

BILBO

BILBO Application

Memory Self-Test Patterns: Writing/Reading 0s, 1s, Walking 0s, 1s Galloping 0s, 1s

Magic Mask Artwork Generator for Integrated Circuits - from U. C Magic Mask Artwork Generator for Integrated Circuits - from U.C. Berkeley Magic is a interactive system for creating and modifying VLSI Circuit Layouts Magic is not a color painting tool, it understands the nature of the circuits you design, and provides additional operations and analysis Magic permits only Manhattan geometry Magic uses composite layers - not simple mask layers Magic provides interactive drc, extraction, and interfaces to IRSIM.

Initial Login

Use PICO to edit .login file

.bash_profile and .login file

1. Add appropriate line to .login and .bash_profile files depending on source ~cad/CAD_HOME/SCRIPTS/newcad.bash 1. Add appropriate line to .login and .bash_profile files depending on account. 2. Then logoff of computer. 3. Finally Logon once again. What should you see? source ~cad/CAD_HOME/SCRIPTS/newcad.tcsh

Appropriate Settings Must have this heading in order to run MAGIC

4. Running MAGIC

Magic Tutorial #1: tut1

tut1

6. Invoking Commands :paint

6. Invoking Commands :grid

Quitting

MAGIC Tutorial #2: tut2a

Creating a Box and using the Cursor Then right mouse button to finish and capture the upper right corner of box. Left mouse button to start box in lower left corner.

Painting using the Middle Mouse Button

tut2a :paint

tut2a :undo

tut2a :redo

tut2b and Selecting

tut2b and More Selecting

tut2c and Labeling

Creating a Cursor Left and Right click at the same spot.

Erasing Labels Select desired area.

Erasing Labels

Inverter Layout in MAGIC

An Inverter with Design Rule Errors Grid spacing. Opening the Palette. Examples of Labeling.

Saving and Extracting MAGIC Files

Extracting MAGIC Layout into SPICE Format Please note: Extract the Magic file The two “base-names” must be the same (inverter)

Mosis scmos 2u parameters. (you get from: CAD_HOME/lib/scmos2um.spice) Extracted by MAGIC and ext2spice Spice3 commands (you must add)

Copy and paste using the left mouse button to highlight the text in PICO then use the right mouse button to copy the highlighted text into the spice3 xterm window. ** This will save you time in the long run.

Printing in MAGIC and SPICE