ECE web page  Courses  Course web pages Introduction to VHDL Course web page: http://ece.gmu.edu/courses/ECE545/index.htm ECE web page  Courses  Course web pages  ECE 545

Research and teaching interests: Kris Gaj Assistant Professor at GMU since Fall 1998 Research and teaching interests: cryptography network security computer arithmetic VLSI design and testing Contact: Science & Technology II, room 223 kgaj@gmu.edu, (703) 993-1575 Office hours: R, W 7:30-8:30 PM T 5:00-6:00 PM

ECE 545 Part of: MS in CpE Digital Systems Design Microprocessor and Embedded Systems MS in EE

Courses Design level Introduction to VHDL Computer Arithmetic VLSI Automation VLSI Test Concepts algorithmic ECE 645 ECE 545 ECE 681 register-transfer ECE 682 gate ECE 586 transistor Digital Integrated Circuits ECE 680 layout Physical VLSI Design MOS Device Electronics devices ECE684

Recommended for students who by the end New MS CpE Course Requirements Recommended for students who by the end of Summer 2004 completed FOUR OR LESS graduate courses towards their MS CpE degree

Core courses There are TWO core courses common for all concentration areas: CS 571 Operating Systems – H. Aydin, S. Setia, C. Snow, project, C/C++ or Java Pros: Prerequisite for many other courses and projects HLL (High Level Language) refresher Offered regularly in Fall and Spring ECE 548 Sequential Machine Theory – K. Hintz, R. Schneider Common theoretical and mathematical foundation used in all concentrations Offered regularly in Spring Not a strong prerequisite for any other course; can be taken any time during the curriculum.

Required courses There are FOUR required courses separate for each concentration area Criteria of choice: Logical sequence of four courses giving a strong foundation for a study, research, and professional position in a given concentration area. All courses will be offered on a regular basis (at least once per year). Substitutions should be allowed only under exceptional circumstances. At least two courses are ECE courses taught by the Computer Engineering faculty, the remaining two courses are chosen from among the most related courses in the EE, CS, and INFS programs. Should include projects, and guarantee the required level of difficulty needed to obtain the CpE degree.

DIGITAL SYSTEMS DESIGN Concentration advisor: Ken Hintz ECE 545 Introduction to VHDL – K. Hintz, K. Gaj, project, VHDL, Aldec/ModelSim, Synplicity/Synopsys ECE 645 Computer Arithmetic: HW and SW Implementation – K. Gaj, project, VHDL, Aldec/Synplicity/Xilinx and Synopsys ECE 586 Digital Integrated Circuits – D. Ioannou ECE 681 VLSI Design Automation – K. Kazi, R. Mehler, project, VHDL, ModelSim and Synopsys

MICROPROCESSOR AND EMBEDDED SYSTEMS Concentration advisor: Peter Pachowicz ECE 511 Microprocessors – P. Pachowicz ECE 545 Introduction to VHDL – K. Hintz, K. Gaj, project, VHDL, Aldec/ModelSim, Synplicity/Synopsys ECE 611 Advanced Microprocessors – D. Tabak ECE 612 Real-Time Embedded Systems – K. Hintz

NETWORK AND SYSTEM SECURITY Concentration advisor: Kris Gaj ECE 542 Computer Network Architectures and Protocols – S.-C. Chang, et al. ECE 646 Cryptography and Computer Network Security – K. Gaj – lab, project, C/C++, VHDL, or analytical ECE 746 Secure Telecommunication Systems – K. Gaj – lab, project, C/C++, VHDL, or analytical INFS 766 Internet Security Protocols – R. Sandhu

COMPUTER NETWORKS Concentration advisor: Brian Mark ECE 528 Random Processes in ECE – J. Gertler ECE 542 Computer Network Architectures and Protocols – S.-C. Chang ECE 642 Design and Analysis of Comp. Comm. Networks – B. Mark – programming assignments Matlab/C++/Java ECE 742 High Speed Networks – B. Mark – analytical project

Elective courses Each student can choose 4 elective courses from a list of electives common for all concentration areas. All elective courses must be approved by the concentration area advisor (in the form of a partial or complete plan of study) prior to registering for these courses.

Recommended for students who by the end Old MS CpE Course Requirements Recommended for students who by the end of Summer 2004 completed FIVE OR MORE graduate courses towards their MS CpE degree

Digital Systems Design ECE 545 Core Courses ECE 586 ECE 548 ECE 584 ECE 645 ECE 680 ECE 681 ECE 682 Required Courses (replacement requires an approval of the concentration area advisor)

Microprocessor and Embedded Systems ECE 511 Core Courses CS 571 ECE 542 ECE 548 CS 540 ECE 611 ECE 612 ECE 641 CS 668 Required Courses (replacement requires an approval of the concentration area advisor)

Concentration Area Advisors (for both old and new degree requirements) DIGITAL SYSTEMS DESIGN: Ken Hintz COMPUTER NETWORKS: Brian Mark NETWORK AND SYSTEM SECURITY: Kris Gaj MICROPROCESSOR AND EMBEDDED SYSTEMS: Peter Pachowicz

ECE 545 Lecture Projects Homework 30 % 30 % Midterm exam 20 % in class 20 % take home 30 %

Midterm exam 1 2 hours 30 minutes in-lab open-books, open-notes practice exams will be available on the web Tentative date: Thursday, October 28th

Midterm Exam 2 take-home 24 hours Tentative date: Thursday, December 9th

Project technologies semi-custom Application Specific Integrated Circuits and Field Programmable Gate Arrays

Levels of design description Algorithmic level Level of description most suitable for synthesis Register Transfer Level Logic (gate) level Circuit (transistor) level Physical (layout) level

Register Transfer Logic (RTL) Design Description Registers … Combinational Logic Combinational Logic Clock

Design Process for ASICs (1) VHDL code VHDL simulator Functional verification Library of standard cells Logic Synthesis Speed without routing Area without routing Netlist

Design Process (2) Netlist Library of Placing & routing standard cells Area with routing Speed with routing Layout

Design process for FPGAs (1) Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds….. Specification (Lab Experiments) VHDL description (Your Source Files) Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; ); end AES_core; Functional simulation Synthesis Post-synthesis simulation

Design process for FPGAs (2) Implementation Timing simulation Configuration On chip testing

CAD software available at GMU (1) VHDL simulators ModelSim (under Unix) available from all PCs in the ECE educational labs using an X-terminal emulator available remotely from home using a fast Internet connection and VNC software. Aldec Active-HDL (under Windows) available in the FPGA Lab, S&T II, room 203

CAD software available at GMU (2) Tools used for logic synthesis Synopsys Design Compiler (under Unix) available from all PCs in the ECE educational labs using an X-terminal emulator available remotely from home using a fast Internet connection and VNC software. Synplicity Synplify Pro (under Windows) available in the FPGA Lab, S&T II, room 203

CAD software available at GMU (3) Tools used for implementation in the FPGA technology Xilinx ISE (under Windows) available in the FPGA Lab, S&T II, room 203