Microprocessor Generations

The First Microprocessor Intel created the first microprocessor 4004 in 1971. Ran at a clock speed of 108KHz Contained 2,300 transistors and was built on a 10-micron process. Then came the Z-80 by Zilog in 1976 used in TRS-80 6502 by MOS Technologies used in Apple-I and II.

The First PC In 1981 IBM introduced the IBM PC, which was based on a 4.77MHz Intel 8088 processor running the Microsoft Disk Operating System (MS-DOS) 1.0 30,000 transistor at 4.77MHz 16 bit internal registers (IA-16) /8 bit external data bus 20 bit address bus could address upto ________Bytes? All Processors are backward compatible, like P4, AMD Athlon, etc.

Generation of Microprocessors First Generation (P1) Second Generation (P2) Third Generation (P3) Fourth Generation (P4) Fifth Generation (P5) Sixth-Generation (P6) Seventh-Generation Processors Eighth-Generation Processors

First Generation (P1) 8088 A 40 pin microprocessor with the attributes of an 8-bit and 16-bit processor. Internally it works with 16 bits but data bus is 8-bits. 20-bit address bus - capable of holding 1 Meg memory. Ran in real mode only Companion Coprocessor - 8087 8086 Same as above only data bus is 8-bits.

Second Generation (P2) 80286 68 pin chip in various packages. Backwards compatible with 8088 but much faster. True 16-bit microprocessor. Designed for multi-user, multi-task. Has special memory protection/management circuitry that protects the various running tasks from each other and the operating system. Operates in two modes: Real Mode - runs single tasks, addresses REAL memory up to 1 Meg. Protected Mode - runs multiple tasks, address up to 16 Meg physical memory, plus it can address virtual memory. Virtual memory is really hard disk space being used as RAM.

Second Generation (P2) 80286 Was available in different clock speeds. Companion Coprocessor - 80287

Third Generation (P3) 80386DX 32-bit (internally & externally) successor to 80286, 132-pins Had to do 16-bit and 8-bit I/O data transfers to keep it compatible with older software and peripherals. Could switch between real and protected memory without a reboot.

Third Generation (P3) This advanced memory management allow for ROM shadowing, moving code out of ROM into faster RAM. New addressing mode was developed called virtual mode. Made the 80386 appear like multiple XT processors so multiple programs could run at once. 80386SX 100 pin chip. Internally the same as a 80386DX, externally had 24-bit address and 16-bit data bus.

Third Generation (P3) Other Flavours of 80386 80386SL: used in laptops, had lower (L) power consumption. Had external 32-bit address bus like DX, but external 16-bit data bus like SX. AM80386SX and DX: AMD manufactured clone. SX was like the SL.

Fourth Generation (P4) 80486DX: 168 pin Included math coprocessor synchronous with main processor and executes in fewer cycles than previous math coprocessors 8KB Level 1 memory cache 90-95% zero wait states Reduced instruction-execution time average of two clock cycles per instruction compared to previous of more than four clock cycles needed Burst-mode memory cycles

Fourth Generation (P4) Other Flavours of 80486: 80486SX: same as DX except there is no coprocessor. Companion coprocessor - 80487 80486DX2: the processor’s internal speed is doubled. 80486DX4: the processor’s internal speed is tripled. CX486SLC: Cyrix processor that is basically a 386SX. CX486DLC:Cyrix processor that is 486DX. CX486DRU2:Cyrix processor that is 486DX2.

Fourth Generation (P4) AMD 486 (5x86) 486 that runs at 133MHz Some 486 motherboards support this chip Similar to Pentium 75 AMD A80486DX2-80SV8B (40MHz x 2) AMD A80486DX4-100SV8B (33MHz x 3) AMD A80486DX4-120SV8B (40MHx x 3)

Fifth Generation (P5) 64-bit data bus 2 separate 8KB internal caches, 1 for instructions, 1 for data superscalar microprocessor, runs multiple instructions simultaneously achieved by pipelining Pipelining breaks instruction cycle into small stages. Each stage is capable of handling many instructions. Two pipelines in pentium, u-pipe and v-pipe Each pipeline has its own ALU

Pipelining Fetching and execution of each instruction is split into many stages, all working in parallel. This allows the processing of up to five instructions to be overlapped.

Pipelining In 8085 there was no pipelining. 8086 had enjoyed the first pipelining. In the 486 the pipeline stage is broken down even further, to 5 stages as follows: 1. fetch (prefetch) 2. decode 1 (two stage decode) 3. decode 2 4. execute 5. register write-back (result goes to EAX)

pipelined vs. nonpipelined execution

Pipelining

Pipelining

heavily pipelining By heavily pipelining the fetching and execution of instructions, many 486 instructions are executed in only 1 clock cycle instead of in 3 clocks as in the 386.

Fifth Generation (P5) Pentium First Generation: 273 pin package 60 & 66 MHz (same speed as motherboard) Same voltage as motherboard Pentium Second Generation: 296 pin package uses 3.3V 90/100/75120/133/150/166/200 MHz could run simultaneously with second processor Symmetric Multi-Processing (SMP)

Fifth Generation (P5) Pentium MMX: Pentium Third Generation Level 1 cache increased from 16 KB to 32 KB External level 2 cache typically 256KB or 512KB Addition of 57 instructions related to multimedia and communication processing. Available in 166/200/266 MHz clock speeds. Requires different voltage level 3.3V for I/O 2.8V for core

Other Fifth-Generation Processors AMD K5 Competes with Classic Pentium Offers an assortment of clock speeds and bus speeds Compatible with most motherboards that supported Pentiums BIOS might need to be upgraded voltage level slightly different - 3.52V Available as: PR75, PR90, PR100, PR120, PR133, PR-166

Other Fifth-Generation Processors Features: 16KB instruction cache Dynamic execution Five-stage RISC-like pipeline FPU Pin-selectable clock multiples of 1.5x & 2x IDT Centaur C6 Winchip Socket-7 compatible Speeds of 180, 200, 225, 240 MHz Not superscalar Slower with multimedia applications and games Smaller, less power consumption

Sixth-Generation (P6) Dynamic Execution Dual Independent Bus Architecture Better Superscalar Design Pentium Pro: 387 pin package has on-board (included with the CPU but not internal) L2 cache, either 256, 512KB or 1MB running at full core speed

Sixth-Generation (P6) Pentium Pro motherboards quite often have sockets for two CPUs Recommended for applications that rely heavily on fast access to cache memory Applications that focus on complex calculations, rather than on servers, need this high-speed performance Does not perform well with older 16-bit legacy applications written for DOS or Windows 3.x

Sixth-Generation (P6) Pentium II Basically the same as Pentium Pro except Has MMX Same Level 1 cache size as Pentium MMX (32K) Package changed from PGA to Single Edge Contact (SEC) cartridge L2 cache of 512KB at half core speed

Sixth-Generation (P6) Pentium II Xeon P6 512KB, 1MB, or 2MB of L2 Cache running at full core speed

Sixth-Generation (P6) Celeron P6 with no L2 cache Packaged in Single Edge Processor Package (SEPP or SEP) almost the same as SEC, missing plastic cartridge cover Celerons above 300 MHz also found in Plastic Pin Grid Array packages (PPGA) it is recommend to get a motherboard with a Slot 1 processor connection as you can install a PPGA using an adapter but you cannot install SEC/SEP in a motherboard with a Socket PGA-370 connection

Sixth-Generation (P6) 7.5 million transistors in 300 MHz and below 19 million transistors above 300-A MHz

Sixth-Generation (P6) Pentium III P6 with SSE 9.5 million transistors 70 new instructions improve on advanced imaging, 3D, streaming audio, video, speech-recognition 9.5 million transistors 512KB of half-core speed L2 cache can cache up to 4GB of addressable memory self-reportable processor serial number Most packaged in Single Edge Contact Cartridge 2 (SECC2)

Sixth-Generation (P6)

Processor Memory-Addressing Capabilities Pentium III / II Xeon larger SEC package connects to motherboard via Slot 2

Other Sixth-Generation Processors Nexgen Nx586 Not pin compatible with Pentiums normally soldered on motherboards Had all fifth-generation features Had sixth-generation feature of branch prediction Had RISC core Was discontinued after merger with AMD AMD-K6 Competes with Pentium II Uses MMX technology In early tests, performed faster than Pentium II in normal business applications

Processor Memory-Addressing Capabilities AMD-K6 Socket 7 interface Sixth-generation internal design, fifth-generation interface AMD-K6-2 Higher clock speeds Higher bus speeds of up to 100MHz 3DNow; 21 new graphics and sound processing instructions AMD-K6-3 256KB of on-die full core speed L2 cache

Processor Memory-Addressing Capabilities Motherboards must be able to support AMD voltages. Must have AMD-K6 processor ready BIOS AMD-K7 (Athlon) Cartridge type packaging, Slot A, not compatible with Pentium II / III motherboards Speeds of 550 MHz and up 128KB L1 cache 512KB L2 cache, running at 1/2, 2/5, or 1/3 processor speed depending model Athlon - Thunderbird has 256K on-processor cache does not support SSE instructions AMD Duron The same as the Athlon with a smaller L2 cache Socketed processor which fits in Socket A.

Processor Memory-Addressing Capabilities Cyrix MediaGX inexpensive soldered on motherboard do not need graphics or sound card - integrated into processor and special motherboard more disposable than upgradable equivalent performance with Pentiums in the same speed range available at 166, 180 MHz, MMX-enhanced available in 200, 233MHz used in Compaq Presario 1220 notebooks

Processor Memory-Addressing Capabilities Cyrix MX/MII compatible with MMX technology achieves higher performance and better value than competitive processors not all motherboards can except this processor

Seventh-Generation Processors Intel Pentium 4 1.3Ghz -1.7Ghz and up Forty-two million transistors Software compatible with previous Intel processors Processor front-side bus runs at 400Mhz Arithmetic logic units run at twice the processor core frequency 20-stage pipeline Very deep out-of-order instruction execution Enhanced branch prediction 20KB L1 cache L2 cache up to 4GB RAM, supports ECC SSE2 instruction set, 144 new instructions Enhanced floating-point unit Multiple low-power states

Eighth-Generation Processor Intel Itanium Designed primarily for servers 733 MHz and 800 MHz speeds Three levels of integrated cache 2 MB or 4 MB of on-cartridge L3 cache running at full-core speed 96 KB of L2 cache 32 KB of L1 cache 266 MHz, 64-bit wide CPU front-side bus with 2.1 GB/second bandwidth 25 million transistors Sixteen TB physical memory addressing Software compatible with previous versions Explicitly parallel instruction computing (EPIC) technology-up to 20 operations per cycle

Processor Memory-Addressing Capabilities Two integer and to memory units that can execute four instructions per clock cycle Two floating-point multiply accumulate units with 82-bit operands FMAC unit is capable of executing two floating-point operations per clock Two additional MMX units Eight single-precision FP operations can be executed every cycle 128 integer registers, 128 floating-point registers, 8 branch registers, 64 predicate registers New cartridge type which includes processor and L3 cache Dedicated cartridge power connector

Processor Upgrades

PC Hardware Links -by Chris Hare http://users.erols.com/chare/main.htm for processor sockets: http://users.erols.com/chare/sockets.htm

Processor Sockets http://users.erols.com/chare/sockets.htm Various 486 Sockets - Socket 1, 2, 3, and 6. http://support.intel.com/support/processors/overdrive/pentium/20284.htm Various Pentium Sockets - Socket 4, 5, 7, and 8. http://support.intel.com/support/processors/overdrive/pentium/20236.htm

Pentium® 4 processors - Comparison Chart http://www.intel.com/support/processors/pentium4/p4compare.htm

PC Hardware Links -by Chris Hare http://users.erols.com/chare/main.htm for processor sockets: http://users.erols.com/chare/sockets.htm