ECE 3430 – Intro to Microcomputer Systems ECE 3430 – Introduction to Microcomputer Systems University of Colorado at Colorado Springs Lecture #13 Agenda Today: Interrupts (Internal and External) Interrupt Service Routines (ISRs) Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2009

ECE 3430 – Intro to Microcomputer Systems Interrupts Interrupt Request (IRQ) - An event that stops normal program operation - Performs a service routine (executes specific code) - Returns the program to normal operation HC11 - The HC11 provides a specific set of interrupts - 16 Hardware - See the pink book for details - 2 Software - 3 Reset Total of 21 interrupt sources Why have interrupts? 1) I/O handling – The CPU can execute the main program and then react to incoming data—rather than periodically testing for data (polling). CPU Data in Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2009

ECE 3430 – Intro to Microcomputer Systems Interrupts 2) Software Errors – A program encounters errors for many different reasons (HW, SW). We need to handle these gracefully instead of letting the program run crazy. 3) Perform Periodic Tasks - Anything that needs to occur at a pre-defined frequency is done with an interrupt. This ensures more precise timing. (ex, update a clock each second) 4) Multitasking - We can time-share between multiple programs by using an interrupt to indicate when to switch to the next program. Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2009

ECE 3430 – Intro to Microcomputer Systems Interrupts Interrupts can be classified as: Externally or Internally Generated Maskable or Non-Maskable Edge or Level Sensitive (Applies to Externally-Generated Interrupts) External interrupts: In this course are interrupts generated by devices external from the HC11 microcontroller. IRQ, XIRQ, and RESET input pins (active-low). A hardware device pulls one of these inputs low to interrupt the HC11. Internal interrupts: In this course are interrupts generated by software (SWI) or on-chip peripheral devices. On-chip peripheral devices can interrupt the CPU. Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2009

ECE 3430 – Intro to Microcomputer Systems Interrupts Maskable Interrupts - Some interrupts can be ignored: “Maskable Interrupts” - Some interrupts CANNOT: “Non-Maskable Interrupts” (NMI) Notation (IRQ = Interrupt Request) - Pending - When an interrupt occurs, but has not been serviced by the CPU. - Service - Executing the code to perform what the interrupt wants done. - Service Routine - The code that executes when the interrupt is serviced. (ISR = Interrupt Service Routine) Priority - Interrupts can occur simultaneously. - Some interrupts are more important than others (i.e., a fire alarm). - Higher priority interrupts are chosen over lower priority interrupts. Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2009

ECE 3430 – Intro to Microcomputer Systems Interrupts CPU Operation When an Interrupt Occurs 1) Complete the currently-executing instruction. 2) Save program counter on stack (marks return address). 3) Save CPU registers/status on stack (CCR, ACCA, etc…). 4) Identify the cause of the interrupt. 5) Retrieve the starting address of the ISR (where in memory the code resides). 6) Adjust PC and execute the interrupt service routine (ISR). 7) Restore the CPU registers/status and program counter from stack. 8) Adjust PC and resume interrupted program. Interrupt Vector - The starting address of the ISR - An ISR is written very similar to a subroutine. The starting address is given a label: Ex) ISR1: <code…> $E000 MAIN $E00X SUB1 $E00X SUB2 $E00X ISR1 Interrupt Vector Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2009

ECE 3430 – Intro to Microcomputer Systems Interrupts Interrupt Vector Table - Predefined address that hold the interrupt vectors (ISR addresses). - Each HC11 interrupt has a spot in the interrupt vector table. Ex) The reset is an interrupt. We already know how to initialize its interrupt vector: ORG $FFFE RESET: FDB $E000 “Interrupt Vector” = $E000 “Interrupt Vector Table address” = $FFFE - When the reset interrupt occurs, the PC is loaded with the data that resides in $FFFE and $FFFF. - The HC11 knows to look at this address. - The PC is loaded with this value and code is executed beginning there. - In our case, we use $E000. - The same process is used for other IRQs. - When interrupt occurs, PC = Interrupt Vector. $FFFE $E0 $FFFF $00 Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2009

ECE 3430 – Intro to Microcomputer Systems Interrupts Interrupt Programming (1 of 3) There are 3 steps that must be done to use interrupts: 1) Initialize the “Interrupt Vector Table” Ex) ORG $FFFE FDB $E000 ORG $FFF2 FDB IRQ_ISR NOTE: Generally speaking, it is good practice to initialize all vector table locations even if you aren’t explicitly using them. This way the behavior is predictable if an interrupt occurs that you weren’t planning to handle. Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2009

ECE 3430 – Intro to Microcomputer Systems Interrupts Interrupt Programming (2 of 3) 2) Write Service Routine - This is the same as writing a subroutine, EXCEPT instead of RTS we use RTI “Return from Interrupt”. We also don’t need to use the do-no-damage paradigm because the system already does it for us. No need to do push and pull operations to preserve the caller’s programming model registers. Ex) ORG $E000 MAIN: … … SUB1: … RTS ISR1: … RTI NOTE: It is perfectly acceptable for an interrupt service routine to call subroutines. SCI_IRQ: JSR SUB1 Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2009

ECE 3430 – Intro to Microcomputer Systems Interrupts Interrupt Programming (3 of 3) 3) Enable Interrupts There are two types of flags that turn on/off interrupts: Global = Will enable multiple interrupts (I-flag, X-flag, or “always on”) Local = Will enable individual interrupts. Set bits in control registers. The control registers are mapped to memory locations $0000- $003F in our HC11. - Some interrupts have global and local enable bits. - Some interrupts have only a global enable bit. - Some interrupts are always enabled. (See the “Interrupt Vector Assignments” table in the pink book) Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2009

ECE 3430 – Intro to Microcomputer Systems Interrupts The Stack and Interrupts - When an interrupt occurs, the status of the CPU is stored on the stack. - The stack must be initialized prior to the first interrupt or you will have major problems. - 9 bytes are pushed onto the stack automatically by the hardware when an IRQ occurs. - For this reason, interrupts have latency associated with them. - The RTI instruction will pull all of this info off of the stack and return the program to normal operation. Note that all CPU state information is automatically pushed so you don’t need to! SP <empty> $00F7 $00F8 $00F9 $00FA $00FB $00FC $00FD $00FE $00FF CCR B A X-high X-low Y-high Y-low PC-High PC-low Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2009

ECE 3430 – Intro to Microcomputer Systems Interrupts Maskable Interrupts - The “I” flag in the CCR is a global enable for a group of interrupts called maskable interrupts. - The “I” bit will enable/disable “global interrupts” for this group. I = 0, ENABLE global maskable interrupts Use CLI I = I, DISABLE global maskable interrupts Use SEI Non-Maskable Interrupts (NMI) - Interrupts that are not classified as maskable are called non-maskable interrupts. - The “X” flag in the CCR is a global enable for the XIRQ external interrupt. - Why is it non-maskable if there is an enable bit? It is initially masked off on reset. Software can clear the X bit (using a TAP instruction)—but once the bit is cleared, it cannot be set again by software. Hence, the interrupt is non-maskable once unmasked the first time. - Other non-maskable interrupts in the system are not effected by the “X” flag. Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2009

ECE 3430 – Intro to Microcomputer Systems Interrupts HC11 Interrupt: CCR Global Mask: Local Mask: RESET (external) <none> <none> COP Clock Monitor <none> CME COP Failure <none> NOCOP Illegal Opcode <none> <none> SWI <none> <none> XIRQ (external) X-bit <none> IRQ (external) I-bit <none> Real-Time Interrupts I-bit RTII Timer Input Capture 1 (IC1) I-bit IC1I Timer Input Capture 2 (IC2) I-bit IC2I Timer Input Capture 3 (IC3) I-bit IC3I Timer Output Compare 1 (OC1) I-bit OC1I Timer Output Compare 2 (OC2) I-bit OC2I Timer Output Compare 3 (OC3) I-bit OC3I Timer Output Compare 4 (OC4) I-bit OC4I IC4/OC5 I-bit I4O5I Timer Overflow I-bit TOI Pulse Accumulator Overflow I-bit PAOVI Pulse Accumulator Input Edge I-bit PAII SPI Serial Transfer Complete I-bit SPIE SCI Serial System I-bit <multiple flags> Highest Priority Reset Non-Maskable Software Hardware Maskable Lowest Priority Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2009

ECE 3430 – Intro to Microcomputer Systems Interrupts Interrupt Priority Promotion - There are 15 interrupts that are enabled when the I-flag is cleared (see blue on previous slide). - Of these, 14 of the interrupts have local flags as well. (Except IRQ) - The 15 interrupts have a priority associated with them. Higher priority interrupts cannot be interrupted by lower priority interrupts. - Of these 15 interrupts, one can be “promoted” so that it has the highest, maskable interrupt priority. This is done by writing to the HPRIO control register. This register can only be written to when the maskable interrupts are disabled (I bit is set). So first you disable them (SEI), then store a value to the HPRIO control register, then enabled them (CLI). Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2009

ECE 3430 – Intro to Microcomputer Systems Interrupts When an XIRQ interrupt occurs, the X and I bits in the CCR are set to inhibit further interrupts. When any maskable interrupt occurs, only the I bit in the CCR is set. The CCR interrupt flag modification occurs after the programming model registers are pushed to the stack. When the RTI instruction executes, the contents are pulled from the stack and the interrupt flags are restored to their previous state. Any non-maskable interrupt with priority higher than XIRQ can always interrupt the CPU—even if a XIRQ or maskable ISR is currently executing. Unless the programmer explicitly clears the I-bit after entering a maskable ISR (using the CLI instruction), no maskable interrupts (even at a higher priority level) can interrupt the ISR in progress. When the ISR completes, the highest pending interrupt will get the attention of the CPU. Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2009

ECE 3430 – Intro to Microcomputer Systems Interrupts Interrupt service routines (ISR) should do the minimum amount of work required to eliminate the interrupt. Interrupt service routines should be short, sweet, and to the point! GET IN CLEAR INTERRUPT GET OUT Ex) Assume an external device asserts the IRQ line to tell uC it has some data for it. The ISR should interrogate the device to determine what it needs to do to make the device stop interrupting. Generally, the uC would perform a set of operations on the device. The device releases the IRQ line in response to these operations. If the uC needs to do more work in response to the interrupt, that work should be done outside of the ISR. Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2009

ECE 3430 – Intro to Microcomputer Systems Interrupts Most of the productive work a uC or uP does should be done outside of interrupt service routines. Spending too much time in interrupt service routines can severely hurt the system performance! When servicing an interrupt generated by an on-chip peripheral device, data is typically written to control registers ($0000-$003F) to cause the on-chip peripheral device to de-assert the interrupt. Extended ISR responsibilities are carried out by a deferred procedure (perhaps the main loop). Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2009

ECE 3430 – Intro to Microcomputer Systems Interrupts External interrupts can be edge sensitive or level sensitive. Edge sensitive interrupts trigger on a rising or falling edge of the interrupt pin. When the ISR is complete, another interrupt does not fire until another edge is detected. Level sensitive interrupts trigger on an active logic level. When the ISR is complete, another interrupt will immediately fire if the interrupt line is still asserted. HC11 specific: RESET: Level sensitive XIRQ: Level sensitive IRQ: Can be either level or edge sensitive depending on how it is configured (by default is level sensitive). RESET, XIRQ, and IRQ are also active-low. Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2009

ECE 3430 – Intro to Microcomputer Systems Specific Interrupts IRQ - An external pin of the HC11 (we have access to it on the MicroStamp). - In the lab, we connected an active-low push button configuration. When the button is pressed, IRQ is asserted low. When the button is released, the IRQ is de-asserted. - Since IRQ is a maskable interrupt, the I flag must be clear in the CCR. - There is no local interrupt enable for IRQ. Ex) Write an ISR that sets PA4 when IRQ is asserted: ORG $FFF2 ; setup interrupt vector table entry for IRQ FDB IRQ_ISR ORG $FFFE ; setup interrupt vector table for external RESET FDB $E000 ORG $E000 SEI ; ensure I-bit is set (maskable interrupts disabled) LDS #$00FF ; initialize stack pointer CLI ; enable maskable interrupts MAIN: BRA MAIN IRQ_ISR: LDAA PORTA ; set only PA4 to 1 (don’t change other bits) ORAA #%00010000 STAA PORTA RTI Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2009

ECE 3430 – Intro to Microcomputer Systems Remember (Important) All interrupts are assigned a priority. If multiple interrupts occur simultaneously, the highest priority ISR is chosen first and so on down to the lowest priority. A periodically-occurring high-priority interrupt can starve lower-priority interrupts (and the main loop) from receiving CPU time! All non-maskable (red in previous slide) interrupts will always interrupt maskable (blue in previous slide) interrupts. Maskable interrupts can only interrupt other maskable interrupts if an interrupt with a strictly higher priority level interrupts and the programmer cleared the I flag in the CCR when entering the lower-priority ISR. Otherwise higher-priority maskable interrupts have to wait on the lower-priority to finish first! Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2009