Real time systems RTS Engineering

RTSs Engineering Two dimensions: Designing, coding and analyzing RT code such it executes in the required interval Threads usage Memory management Synchronization Events and Interrupts Clock and time management Ensuring that resurces such as CPU are allocated so RT activities get enough time and resources to meet their deadlines Scheduling

RT Operating Systems Slides below based on Laplante (chapter 3) RT Kernels Scheduling Intertask Communication and Synchronization Memory Management

RT Kernels Process or Task: Thread: Abstraction of a running program Logical unit of work scheduled by the operating system Represented as a data structure: state of execution, identity, attributes, associated resources Thread: Lightweight process Shares resources with other processes or threads Reside within some process and make use of the resources of that process

RT Kernels Kernels functions related to tasks: Scheduling: which task to run next in a multitasking environment Dispatching: switches the tasks contexts Intercommunication and Synchronization: ensures that the tasks can cooperate

Taxonomy of RT OS layers

Pseudo-kernels Obtain multitasking even if: Techniques: Do not use interrupts No operating system around Techniques: Polled Loops Synchronized Pooled Loops Cyclic Executives State Driven Code Coroutines

Polled Loops Used for fast response to events coming from a single device Repetitive loop testing a flag indicating if the event occurred: while(true){ if (eventOccured){ processData(); eventOccured = false; } Works well when: A single processor is dedicated to handling IO fro some fast device The overlapping of events is not allowed or is minimized

Synchronized polled loops Uses a fixed clock interrupt to pause between the time the event was triggered and the event processing while(true){ if (eventOccured){ pause(20); //wait 20 ms processData(); eventOccured = false; } Ex: switch bounce

Advantages/Disadvantages Pooled loops are simple to develop and analyze, thus easy to guarantee response time Good at handling high speed data channels when the events occur at widely dispersed intervals and the processor is dedicated to the data channel Fails on bursts Not sufficient to handle complex systems Waste CPU

Cyclic Executives A list of tasks called in a continuous loop: while(true){ Process1(); Process2(); … ProcessN(); } Round robin fashion The same process may appear multiple times in the list Intertask communication and synchronization can be implemented through global variables or task parameters Variations in the list of tasks are possible by maintaining the task list as a list of pointers to tasks. Ineffective for more complex RT systems as the duration of tasks is hard to control

State Driven Code Allows for suspending the execution of a task by using nested if-then statements, case structures or finite automata. The task will stay into a stable state until restarted. Work well in conjunction with cyclic executives and coroutines. Not all processes are naturally expressed as finite state automata.

Coroutines Also called cooperative multitasking Requires usage of the state driven code in a task in order for the task to be split in phases; After each phase a central dispatcher is called which switches to the next task in a round robin fashion. Communication is done through global variables

void process_a(void) { for(;;) { switch(state_a) case 1: phase_a1(); break; case 2: phase_a2(); case 3: phase_a3(); case 4: phase_a4(); case 5: phase_a5(); } void process_b(void) { for(;;) { switch(state_b) case 1: phase_b1(); break; case 2: phase_b2(); case 3: phase_b3(); case 4: phase_b4(); case 5: phase_b5(); }

Advantages/Disadvantages No hardware interrupts Requires programmers giving control to the dispatcher at known intervals in order for the fairness scheduling to happen Communication through global variables is not desirable Processes cannot be always decomposed uniformly

Interrupt Driven Systems Tasks scheduled through hardware/software interrupts Dispatching performed by the interrupt handling routines Techniques: Interrupt service routines Context switching Preemptive priority systems Hybrid Systems The task control block model

Interrupt Service Routines Hardware Interrupt: A signal generated by a peripheral device and sent to the CPU. CPU executes an Interrupt Service Routine (ISR) to perform appropriate actions Software Interrupt: similar to the hardware interrupt but comes from the running code Exception: internal interrupt triggered by a program performing an unexpected or an illegal operation

Processing Interrupts Asynchronous, can happen at any time The program is suspended while CPU invokes ISR The application developer is often required to write the ISR for a specific type of hardware interrupt The developer has to understand the CPU state and to preserve everything needed in addition to the general registers Access to the shared resources within an ISR is usually controlled by disabling/enabling interrupts around any code accessing that resource

Processing Interrupts Synchronization is not possible inside an ISR as it cannot wait indefinitely for a resource It is important to minimize the time the interrupts are disabled Reentrant code: code which is safe to be executed simultaneously from two contexts ISR is reentrant if the same interrupt can occur while still processing a previous occurrence The machine context prior to ISR has to be restored after ISR completion.

Context Switching The process of saving and restoring sufficient information for a RT task so that it can be resumed after it is interrupted Usually saved on the stack Context switching time is important when evaluating the response time Contexts include: General registers The program counter Coprocessor registers (if available) Memory page register Images of the memory-mapped I/O locations

Context Switching Interrupts has to be disabled during the critical context switching period The stack model for context switching: Mostly used in embedded systems Each interrupt handler is associated with a hardware interrupt invoked by the CPU based on a stored interrupt vectors table The context is saved to a memory area (single interrupt systems) or to the stack.

void int2(void) /. interrupt handler 2. / { save(context); / void int2(void) /* interrupt handler 2 */ { save(context); /* save context on stack */ task2(); /* execute task 2 */ restore(context); /* restore context from stack */ } void int3(void) /* interrupt handler 3 */ task3(); /* execute task 3 */ restore(context); /* restore context from stack */ void main(void) /*initialize system, load interrupt handlers */ { init(); while(TRUE); /* infinite wait loop */ } void intl (void) /* interrupt handler 1 */ save(context); /* save context on stack */ task1(); /* execute task 1 */ restore(context); /* restore context from stack */

Preemptive-Priority Systems A higher-priority task is said to preempt a lower-priority task if it interrupts the lower-priority task Preemptive-priority systems: Systems that use preemption schemes instead of round-robin or first-come-first-served scheduling Fixed priority vs. dynamic priority Starvation: lower priority tasks do not run Rate monotonic systems: special class of fixed-rate preemptive-priority interrupt-driven systems where priorities are assigned so that the higher the execution frequency, the higher the priority

Hybrid Systems Systems processing interrupts occurring both at fixed rate and sporadically Common in embedded applications when sporadic interrupts handle critical errors requiring immediate attention Also found as combinations of round robin scheduling (tasks with the same priority) and preemption (higher priority tasks) Types: Foreground/background systems Background processing Initialization Real-time operation Full-featured real-time operating systems Task Control Block Model

Foreground/Background Systems Adds some processing in the polled loop which is the main program: background work The most common architecture for embedded applications Involve a set of interrupt driven or RT processes called the foreground and a collection of noninterrupt-driven processes called the background. The foreground tasks run in round-robin, preemptive priority, or hybrid fashion. The background task is fully preemptable by any foreground task (the lowest priority task in the system)

FgBg Systems Architecture

RT Solutions vs FgBg Systems All real-time solutions are just special cases of the foreground/background systems: The polled loop is simply a foreground/background system with no foreground, and a polled loop as a background. State-driven code is a foreground/background system with no foreground and phase-driven code for a background. Coroutine systems are a more complicated background process. Interrupt-only systems are foreground/background systems without background processing.

Background processing tasks Count statistics for the foreground processes Monitor the foreground processes Testing the CPU instruction set (robust systems) Updates the display, log to printers or other interfaces

Initialization First part of the background process: Disable interrupts Set up interrupt vectors and stacks Perform self-test Perform system initialization Enable interrupts

Real Time Operation Foreground/background systems typically have good response times, since they rely on hardware to perform scheduling. Drawbacks: interfaces to complicated devices and networks must be written. This procedure can be tedious and error-prone. best implemented when the number of foreground tasks is fixed and known a priori. Although languages that support dynamic allocation of memory could handle a variable number of tasks, this can be tricky. the foreground/background system is vulnerable to timing variations, unanticipated race conditions, hardware failures, and so on (similar to the interrupt only systems).

Full Featured RT Operating Systems The foreground/background solution can be extended into an operating system by adding additional functions such as network interfaces, device drivers, and complex debugging tools Rely on a complex operating system using round-robin, preemptive priority, or a combination of both schemes to provide scheduling; The operating system represents the highest priority task: kernel or supervisor

The Task-Control Block Model The ISR model allows for a determined number of tasks to exists. TCB Model allows for variable number of tasks Used in interactive on-line systems where tasks associated with users manifest a great dynamism Added overhead to the scheduler Each task is associated with a data structure called the Task Control Block TCBs are placed in a linked list in order to be managed by the scheduler

Task Control Block

Task states

Task management RT OS: highest priority task Each hardware interrupt invokes the RT OS OS maintains a linked list of TCBs for Ready tasks and another list for the tasks in the Suspended state OS maintains a list with the resources and a table with resources requests OS checks the ready list to see if the next task is eligible for execution If eligible, the TCB of the currently executing task is placed at the end of the ready list The TCB of the eligible task is removed from the list and its execution begins The updates on the “status” of a TCB drive the way the tasks are managed