Operating Systems Engineering

Slides:



Advertisements
Similar presentations
CS 4284 Systems Capstone Godmar Back Processes and Threads.
Advertisements

Using VMX within Linux We explore the feasibility of executing ROM-BIOS code within the Linux x86_64 kernel.
Chapter 6 Limited Direct Execution
IA32 Paging Scheme Introduction to the Pentium’s support for “virtual” memory.
CS591 (Spring 2001) The Linux Kernel: Signals & Interrupts.
Operating Systems: Segments 1 Segmentation Hardware Support single user program system: – wish somehow to relocate address 0 to after operating system.
IA-32 Processor Architecture
Page-Faults in Linux How can we study the handling of page-fault exceptions?
Context Switch Animation Another one by Anastasia.
‘struct sigcontext’ On using Linux’s signaling mechanism for debugqing application programs.
X86 segmentation, page tables, and interrupts 3/17/08 Frans Kaashoek MIT
Project 2 Roadmap. Background – Context Switching One processor and multiple threads running concurrently – How?!! Give each thread a small time quantum.
Context switch in Linux
PC hardware and x86 3/3/08 Frans Kaashoek MIT
Linux Operating System
Administrative Overview 6 Projects Design Review: Monday before 6:30pm Lab Friend Center 010 (“Fishbowl”)
UNIT 2 Memory Management Unit and Segment Description and Paging
CEG 320/520: Computer Organization and Assembly Language ProgrammingIntel Assembly 1 Intel IA-32 vs Motorola
6.828: PC hardware and x86 Frans Kaashoek
Windows Kernel Internals Traps, Interrupts, Exceptions
Multitasking Mr. Mahendra B. Salunke Asst. Prof. Dept. of Computer Engg., STES SITS, Narhe, Pune-41 STES Sinhgad Institute of Tech. & Science Dept. of.
1 CSE451 Architectural Supports for Operating Systems Autumn 2002 Gary Kimura Lecture #2 October 2, 2002.
Virtual 8086 Mode  The supports execution of one or more 8086, 8088, 80186, or programs in an protected-mode environment.  An 8086.
15-410, S’ Hardware Overview Jan. 19, 2004 Dave Eckhardt Bruce Maggs L04_Hardware “Dude, what were you thinking?”
LINUX System : Lecture 7 Process Bong-Soo Sohn Lecture notes acknowledgement : The design of UNIX Operating System.
Operating Systems Engineering Based on MIT (2012, lec3) Recitation 2: OS Organization.
Chapter 4 Process Abstraction Chien-Chung Shen CIS, UD
Microprocessor system architectures – IA32 tasks Jakub Yaghob.
6. HAL and IDT ENGI 3655 Lab Sessions. Richard Khoury2 Textbook Readings  Interrupts ◦ Section  Hardware Abstraction Layer ◦ Section
Chapter 2 The Microprocessor Architecture Microprocessors prepared by Dr. Mohamed A. Shohla.
Assembly 08 Interrupts. Introduction Interrupts are similar to procedures –They are used to alter a program’s control flow –The interrupt service is also.
10. Epilogue ENGI 3655 Lab Sessions.  We took control of the computer as early as possible, right after the end of the BIOS  Our multi-stage bootloader.
What You Need to Know for Project Three Steve Muckle Wednesday, February 19 th Spring 2003.
Information Security - 2. Task Switching Every process has an associated Task State Segment, whose starting point is stored in the Task register. A task.
Lecture 7 Interrupt ,Trap and System Call
What You Need to Know for Project Three Dave Eckhardt Steve Muckle.
Virtualizing the CPU: Processes 1. How to provide the illusion of many CPUs? CPU virtualizing – The OS can promote the illusion that many virtual CPUs.
What You Need to Know for Project Three
Stack Operations Dr. Hadi AL Saadi.
Assembly function call convention
Introduction to Operating Systems
Homework / Exam Return and Review Exam #1 Reading Machine Projects
Assembly language.
C function call conventions and the stack
Interrupts and signals
Microprocessor and Assembly Language
CS-401 Computer Architecture & Assembly Language Programming
Anton Burtsev February, 2017
Protection of System Resources
Anton Burtsev February, 2017
ICS143A: Principles of Operating Systems Lecture 13: Context switching
Anton Burtsev February, 2017
CS 3305 System Calls Lecture 7.
143A: Principles of Operating Systems Lecture 5: Address translation
Basic Microprocessor Architecture
x86 segmentation, page tables, and interrupts
Introduction to Intel IA-32 and IA-64 Instruction Set Architectures
CS 301 Fall 2002 Computer Organization
CSE 451: Operating Systems Spring 2012 Module 6 Review of Processes, Kernel Threads, User-Level Threads Ed Lazowska 570 Allen.
CSE 153 Design of Operating Systems Winter 18
The Microprocessor & Its Architecture
Tutorial No. 11 Module 10.
Computer Architecture CST 250
CSE 451: Operating Systems Autumn 2001 Lecture 2 Architectural Support for Operating Systems Brian Bershad 310 Sieg Hall 1.
REGISTER ORGANIZATION OF 80386
Low-Level Thread Dispatching on the x86
System Calls System calls are the user API to the OS
Interrupts and System Calls
Computer Architecture and System Programming Laboratory
Register Allocation Harry Xu CS 142 (b) 05/08/2018.
Presentation transcript:

Operating Systems Engineering Recitation 3: Interrupts, Exceptions Based on MIT 6.828 (2012, lec5)

Stacks in the System Where can our code run? User mode Kernel Mode Same stack for user and kernel? How many user stacks? 1 or many? 1 for each process? More? How many kernel stacks? Why would you need more than 1?

Mode Transitions What mode transitions do we have? User  Kernel System calls Interrupts Exceptions Kernel  User Kernel  Kernel Context switch

Mode Transitions Why is user  kernel transition delicate? What do we need to maintain? Need to maintain isolation Need to maintain transparency

Reminder: x86 Privilege Levels Controlled by CPL Bottom two bits of the cs register CPL=0 – kernel mode – privileged CPL=3 – user mode – not privileged cs: CPL

System Calls What needs to happen in a system call? Save user state Transition to kernel (stack, CPL=0) Choose kernel entry point Get system call arguments

Interrupt vectors Where does “int $0x30” jump to? $0x30 is an interrupt vector A vector is an allowed kernel entry point x86 has 256 vectors different uses (devices, exceptions, syscalls…) Each vector in an index in the IDT

Interrupt Descriptor Table Table of all interrupt descriptors Pointer to by the IDTR register Contains interrupt / trap gates

Interrupt Handling Flow Fetch vector's descriptor from IDT If segment selector's PL < CPL: Load SS and ESP from TSS Push user SS Push user ESP Push user EFLAGS Push user CS Push user EIP Clear some EFLAGS bits (which?) Set CS and EIP from IDT

Interrupt Handling in xv6 Entry points – vectors.pl (sheet 29) Kernel SS and ESP setup – switchuvm() in vm.c (sheet 17) IDT setup – tvinit() in trap.c (sheet 30) Entry point calls alltraps, which calls trap Who initialized and passed trapframe to trap?

struct trapframe Where does each value come from? struct trapframe { uint err; uint edi; uint esi; uint eip; uint ebp; ushort cs; uint oesp; ushort padding5; uint ebx; uint eflags; uint edx; uint ecx; uint esp; uint eax; ushort ss; ushort padding6; ushort gs; ushort padding1; }; ushort fs; ushort padding2; ushort es; ushort padding3; ushort ds; ushort padding4; uint trapno; Where does each value come from?

System Call Handling If tf->trapno == T_SYSCALL (0x40) – trap() calls syscall() (sheet 33) Syscall number determined by tf->eax Where is this value set? No value returned to trap – where is system call return value? How are parameters passed?

Handling Other Interrupts Other interrupts are handled the same Can be handled internally by kernel User can subscribe to some POSIX Signals Can happen in kernel Trapframe is a bit different, how?

Device Interrupts Hardware generated Different vector for different devices Timer Console Disk Network …

Fork fork() – proc.c (sheet 23) allocproc() – proc.c (sheet 22)