AACD’17 Workshop Report: Advanced-node Analog Circuit Design Edinei Santin CERN, April 10th 2017

About the AACD workshop The AACD workshops are a high quality series of events held annually since 1992 “The aim of the workshop is to bring together a restricted group of less than 100 people, who are personally advancing the frontiers of analog circuit design, and to brainstorm on new possibilities and future developments” The workshop covers three different topics during three consecutive days Each day of the workshop consists of six tutorial lectures, ample discussion time and a final panel discussion Proceedings are available at the workshop. Afterwards a book is edited of the revised proceedings. … see more visiting the workshop website

AACD’17 in Eindhoven/NL, March 28-30 2017 Organized by Holst Centre / imec the Netherlands Three topics covered this year: Hybrid ADCs, Chairman: Pieter Harpe (T.U. Eindhoven) Sensor design for IoT, Chairman: Kofi Makinwa (T.U. Delft) Sub-1V & advanced-node analog circuit design, Chairman: Andrea Baschirotto (University of Milan-Bicocca)  159 participants from all over the world … my presentation will focus on this only!

3rd day program … will focus on this talk! DACs & ADCs in 28nm vs 14 nm SAR & NS these works prove that it is possible to do analog, mixed-signal, and RF design in advanced nodes  time domain digital-assisted analog, new ideas, ... Mark Liu, TSMC [1]:  “Bulk semiconductor technology has been enhanced for 30 years and is used by Intel and Samsung,” the world’s two largest chip makers  “FD-SOI will always be the technology of the future,” he quipped

Eindhoven/NL  Birthplace of Philips in 1891 Anton Philips, the youngest son Philips at the beginning… Ladies importance! 3rd day panel discussion…

FinFET original purpose (1/..) Address the need for improved gate control to suppress IOFF, DIBL and process‐induced variability for Lg < 25 nm [5] It has taken ~10 years to bring “3‐D” transistors into volume production [5] A. Loke [6] DIBL = Drain-Induced Barrier Lowering  short-channel effect (SCE) in MOSFETs referring originally to a reduction of threshold voltage, VT, of the transistor at higher drain voltages, VD, i.e. VT(VD)

FinFET original purpose (2/..) Address the need for improved gate control to suppress IOFF, DIBL and process‐induced variability for Lg < 25 nm [5] It has taken ~10 years to bring “3‐D” transistors into volume production [5] “fin” A. Loke [6] DIBL = Drain-Induced Barrier Lowering  short-channel effect (SCE) in MOSFETs referring originally to a reduction of threshold voltage, VT, of the transistor at higher drain voltages, VD, i.e. VT(VD)

Scaling innovations A. Loke [6]

Scaling innovations A. Loke, “16/14nm analog/mixed-signal design is about understanding all the scaling techniques that led to FinFET as much as understanding FinFET itself” A. Loke [6]

Design considerations (1/..) More Ieff and less Ileak for a given footprint  Quantized channel width / OK for analog since it allows enough gm granularity Less DIBL  Better Rout, 3x enhancement over planar 28nm technology Essentially no body effect  ΔVT < 10mV Higher Rs & Rd spread resistance  Problem of landing contacts on 3D transistor Lower Cj  but higher Cgd & Cgs  coupling to the gate Higher Rwell / Mismatch depends on several factors But improves compared to planar technologies 

Design considerations (2/..) Stack “unit” MOSFETs in series & in parallel to achieve desired W/L Routing parasitics start to become dominant “Sliced-based” design & layout e.g. differential pair  70,000 transistors! Many stacked devices blow up netlist size and simulation time, if appropriate care is not taken into account. Possible remedies: Customized p-cells First-order models Automation, see e.g. P.-H. Wei [7] More wiring R & C parasitics

Conclusions FinFETs address the need for improved gate control to suppress IOFF, DIBL and process‐induced variability FinFETs are improved in comparison to bulk transistors Main stream technologies will be FinFET, but only a few mixed circuits (PLLs, DACs, ADCs) will be placed on these digital systems Analog functionality costs more in new node. Overall system cost, not technology cost Partition options: board vs package (SoC/SiP) integration Can small research institutes and universities play the FinFET game?

Thank you for your attention!

References [1] R. Merritt, “TSMC Tips 7+, 12, 22nm Nodes,” in EE Times, Mar. 2017. [2] A. Loke et al., “Analog/Mixed-Signal Design in FinFET Technologies,” in AACD proceedings, Mar. 2017. [3] L. Dorrer et al., “Analog circuits in 28nm and 14nm FinFET,” in AACD proceedings, Mar. 2017. [4] C. Hu, “3D FinFET: New Structure Rejuvenates Transistor!,” Mar. 2012. [5] T.‐J. K. Liu, “FinFET: History, Fundamentals and Future,” in IEEE Symposium on VLSI Technology, Jun. 2012. [6] A. Loke, “The Journey to FinFETs,” in IEEE MWSCAS, Aug. 2015. [7] P.-H. Wei, “Automated layout generation for analog circuits,” PhD research at Stanford.