A New Logic Synthesis, ExorBDS

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Presentation transcript:

A New Logic Synthesis, ExorBDS Kelsey Muma Department of Electrical Engineering, University of Saskatchewan Seok-Bum Ko ExorBDS

A New Logic Synthesis, ExorBDS Outline Introduction Background ExorBDS Experimental Method and Results Conclusions ExorBDS

Introduction FPGAs Useful for rapid prototyping Excellent re-programmability features Higher cost/logic than ASICs Cannot be as efficient when also trying to be programmable ExorBDS

Introduction Commercial EDA tools provide technology-independent minimization, followed by technology-dependent mapping We believe current EDA tools sub-optimal, particularly for XOR-intensive functions (maybe others as well) ExorBDS

Background Parity Prediction Circuits Basic error checking method Prediction circuit involves XORing all outputs to determine expected parity bit ExorBDS

Background Overview of Xilinx Virtex II Pro Experimental results based on this FPGA (XC2VP2) Contains CLBs Each CLB contains 4 slices Each slice contains 2 4-input LUT 4-LUT: used for comparing methods ExorBDS

ESOP-minimization Often requires fewer product terms/literals than traditional SOP minimization FPGA logic resource usage based on number of inputs, not on Boolean complexity (as in ASICS) An EXOR gate in ASICS requires more area In FPGAs, XOR gate takes same amount of resources as and/or gates ExorBDS

BDD-based Decomposition BDS BDD-based program which decomposes circuits using BDDs as basic data structure Decomposing allows removal of shared nodes, as well as better mapping to FPGA LUT (Decompose circuit, so functions can be grouped into k-input functions) ExorBDS

ExorBDS Includes single stage of ESOP-minimization, followed by a stage of BDD-based decomposition 1. Use Exorcism4 for ESOP-minimization 2. Use BDS for BDD-decomposition ExorBDS

ExorBDS Parity prediction circuit Exorcism4 BDS Basic ExorBDS algorithm Convert benchmark circuit into parity prediction circuit, by changing original outputs to signals, and then XORing these signals to produce single parity output Run Exorcism4 on the parity prediction circuit to obtain minimized ESOP circuit Run BDS on minimized ESOP circuit to decompose circuit Convert to VHDL, synthesize ExorBDS

Experimental Methods Synthesized parity prediction functions of 14 MCNC benchmark circuits using 4 methods: Direct Method (Using commercial EDA tools only) Exorcism4 BDS ExorBDS ExorBDS

Experimental Results Results compared based on following metrics: Area (4-LUT) Delay (max. combinational path delay) Area-Delay Product ExorBDS

Experimental Results* Results of 13/14 benchmark circuits (Misex3 excluded – it is so large, dominates results) *: misex3 excluded ExorBDS

Conclusions These results would allow FPGA designer to have much more logic than the same FPGA using commercial tools Could help bridge the cost/logic gap between FPGA and ASIC ExorBDS

Future Work It is believed such efficiencies can also be extended to arithmetic circuits and error correcting/detecting circuits Analysis of ExorBDS on NON XOR-intensive circuits If results are as good or better, ExorBDS will provide a general solution to synthesis ExorBDS

Questions ? ExorBDS