Status of the FPGA Firmware of the HF FE Tullio Grassi – Univ of Maryland 23 July 2015

Introduction At this moment all HF FPGA designs are supposed to be completed. Rather then listing the working features, i will focus on what is missing or what is not working

igloo2 FPGA Bridge QIE10 CH1 CH24 … QIE card (1) The «fast» signals of the QIE10 chips (sampling clock, reset, data) are handled by the igloo2 FPGAs Individually each QIE channel is handled properly. On certain configurations, a QIE channel is shifted in time by one 40MHz-cycle The problem is not critical The next iteration of the QIE10 chips will behave differently: it will tune the sampling clock internally (same as QIE11) Not clear if it is worth to improve the FPGA for the present version of QIE10. will need to modify the igloo2 FPGAs if we mount the new QIE10 chips

igloo2 FPGA Bridge QIE10 CH1 CH24 … QIE card (2) Bad behavior observed when writing parameters from ngCCM server to the QIE chips. This type of communication goes through the Bridge FPGA, but not through the igloo2 FPGAs. An example is logged on http://cmsonline.cern.ch/cms-elog/869693 Cause of the problem is not clear

igloo2 FPGA Bridge QIE10 CH1 CH24 … QIE card (3) The PCB has been designed to support the power cycle of the igloo2 FPGAs, controlled by the ngCCM server. The goal is to protect the igloo2 from certain radiation effects This needs a modification of the Bridge FPGA. I should be able to do it once i have a stable teststand

ngCCM The main control link is handled by the mezzanine igloo2 FPGA ProASIC3L FPGA #1 FPGA #4 Sec igloo2 Mezz … ngCCM The main control link is handled by the mezzanine igloo2 FPGA Till a few weeks ago the link was working on certain configurations, but was not stable from version to version and from card to card Some improvements in the last few weeks To be verified still missing: Locking of the placement of critical elements in the igloo2

Common to all FPGAs Not critical but preferrable modifications: Force the compiler to use of IO flip-flops when appropriate IOs : reduce slew rate and current drive in order to minimize Simultaneous Switching Noise and power consumption, IOs: set SCHMITT_TRIGGER on lines that could benefit from it (SCL, SDA, etc) Make sure that the system does not degrade after the modifications Need large-scale tests (at least a full crate)

Other notes I have not yet seen the ngCCM server able to program remotely the igloo2 on the QIE card. Stephen achieved it with his private sw, but not reliably. This is a sw task, but it is possible that present FPGA designs are not correct. The ngCCM server has a cashing mechanism: when you ask to access the same FE register twice within a very short time, the server will not access the register the 2nd time. The cashing effect is visible when running with scripts. Some of us got confused by it  Remember that the Slow Control system is just for slow stuff.