Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved. Chapter 7 Transfer Gate and Dynamic Logic Design Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.

7.2 Basic concepts

7.2.1 Pass Transistors

7.2.1 Pass Transistors

7.2.1 Pass Transistors

7.2.2 Capacitive Feedthrough

7.2.2 Capacitive Feedthrough

7.2.2 Capacitive Feedthrough from charge equations (7.1) (7.2) (7.3)

7.2.3 Charge Sharing

(7.4) (7.5) (7.6) 7.2.3 Charge Sharing from total charge equations Final voltage after charge exchange (7.4) (7.5) (7.6)

7.3 CMOS Transmission gate logic

Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved. 7.3 CMOS Transmission Gate Logic Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.

7.3 CMOS Transmission Gate Logic

7.3.1 Multiplexers Using CMOS Transfer Gates

7.3.1 Multiplexers Using CMOS Transfer Gates

7.3.1 Multiplexers Using CMOS Transfer Gates

7.3.1 Multiplexers Using CMOS Transfer Gates

7.3.1 Multiplexers Using CMOS Transfer Gates

7.3.1 Multiplexers Using CMOS Transfer Gates

7.3.2 CMOS Transmission Gate Delays

7.3.2 CMOS Transmission Gate Delays Large-signal resistance (Figure 7.8) NMOS saturation linear PMOS

7.3.2 CMOS Transmission Gate Delays Large-signal resistance (Figure 7.8) PMOS saturation linear NMOS

7.3.2 CMOS Transmission Gate Delays

7.3.2 CMOS Transmission Gate Delays On-resistance All resistance (7.7)

7.3.2 CMOS Transmission Gate Delays

(7.8) (7.9) (7.10) (7.11) 7.3.2 CMOS Transmission Gate Delays Input and output capacitances (7.8) (7.9) (7.10) (7.11)

7.3.2 CMOS Transmission Gate Delays

7.3.2 CMOS Transmission Gate Delays Elmore delay equation

7.3.3 Logical Effort with CMOS Transmission Gates

7.3.3 Logical Effort with CMOS Transmission Gates

7.4 dynamic d-latches and d flip-flops

7.4 Dynamic D-Latches and D Flip-Flops

7.4 Dynamic D-Latches and D Flip-Flops

7.4 Dynamic D-Latches and D Flip-Flops

7.4 Dynamic D-Latches and D Flip-Flops

7.5 Domino logic

7.5 Domino Logic

7.5 Domino Logic

7.5 Domino Logic

7.5 Domino Logic

7.5.1 Logical Effort for Domino Gates

7.5.1 Logical Effort for Domino Gates LE values for inverter size of 8 for the pull-up and 4 for the pull down for the domino circuit (simply 8 )

Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved. 7.5.2 Limitations of Domino Logic Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.

7.5.2 Limitations of Domino Logic Final voltage after charge exchange

7.5.2 Limitations of Domino Logic

7.5.3 Dual-Rail (Differential) Domino Logic

7.5.3 Dual-Rail (Differential) Domino Logic

7.5.3 Dual-Rail (Differential) Domino Logic

7.5.4 Self-Resetting Circuits

7.6 summary

7.6 Summary Capacitive feedthrough and bootstrapping equation Charge-sharing equation Large-signal resistance for CMOS transmission gate