Combinational circuits

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Presentation transcript:

Combinational circuits Changes at inputs propagate at logic speed to outputs Not clocked No internal state (memoryless) Not “combinatorial”

Example 1 I O I0 & ≥1 O I1 & I2

NOT combinational S R - latch (has a state) & & D Q D - flip-flop (clocked, no path)

Combinational logic - can be connected into sequences 1 - can be connected parallel 1 1 1 & 1 1

Combinatorial loop This is OK: 1 But what is this? 1

Combinatorial loop Impossible! Logical nonsense Electrical trouble 1 1 1 Impossible! Logical nonsense Electrical trouble

or form, a combinatorial loop This is a “combinatorial loop” 1 We must never have, or form, a combinatorial loop

How is this usually solved? D Q “The edge-triggered flip-flop!”

The edge-triggered flip-flop! D Q in out Never a combinational path from in to out A memory device, holds the value of “Q” until “clocked” Ignores the value at “in” until “clocked”

Beginners explanation D Q t 1 clock A “rising edge” A “falling edge” Flipflop “samples” its input at the rising edge Flipflop presents that value at the falling edge

Flip flops in the circuit D Q We will put flip flops in our circuit (Good for “breaking” combinational loops) and clock them all with the same clock

Example Never combinational path thru! Assume we have this: t 0 1 D Q At this time the D-FF “senses” the “1” at its input NO PATH! clock = 0 At this time, it lets that “1” appear at its output Never combinational path thru!

Example BAD OK 1 D Q Suppose the flip flop 1 holds a “1”. Let’s clock this circuit...

Example D Q 1 1 Holding Clock “pulse” one “clock cycle”

Example D Q 1 Samples the “0”

Example D Q 1 Already sampled But output hasn’t changed yet!

Example D Q 1 The exact instant that the output changes!

Example Called a logic “delay” D Q 1 A very short time later... ... the circuit becomes stable again Called a logic “delay” (Propagation through the combinational logic)

Example D Q 1 And it stays like that.... ... until the next clocking

Back to combinational logic Zero extend box Sign extend box Controllable sign/zero extend box “Tap box” (pick out fields of bits) Shift left two bits

Zero extend box 16 16 zeroes ! Out[16..31] 16 In[0..15] 16 Out[0..15]

Sign extend box In[15] copied 16 times 16 Out[16..31] 16 In[0..15] 16

Controllable zero / sign extend box 16 & Out[16..31] In[15] 16 In[0..15] 16 Out[0..15]

Tap box Contains no logic circuits Regroup input bits 6 Opcode field 5 Rs field 32 5 Instruction Rt field 5 Rd field 16 Immediate field

Shift left two bits Out bit [2..31*] 32 In bit [0..31] Out bit 1 Out bit 1 Out bit 0 * Two bits lost

Arbitrary logic Given a truth table: Digital design....... Logic A B C D X Y Z 0 0 0 0 1 1 0 0 1 - 1 0 1 - - 1 1 0 1 0 1 Digital design....... Logic A B C D X Y Z

So, it’s enough just to have the truth table..... We have tools to build the “logic box” “Logic synthesis”

The multiplexor Special truth table: Easy to generalise to A B Cont Out 0 - 0 0 1 - 0 1 - 0 1 0 - 1 1 1 Easy to generalise to “A, B, C, D....” A Out B Cont

Shifters Two kinds: logical-- value shifted in is always "0" arithmetic-- on right shifts, sign extend msb lsb "0" Note: these are single bit shifts. A given instruction might request 0 to 32 bits to be shifted!

Combinational Shifter from MUXes Basic Building Block 8-bit right shifter 1 S2 S1 S0 A0 A1 A2 A3 A4 A5 A6 A7 R0 R1 R2 R3 R4 R5 R6 R7 1 sel A B D What comes in the MSBs? How many levels for 32-bit shifter? What if we use 4-1 Muxes ?

General Shift Right Scheme using 16 bit example (0,1) S 1 (0, 2) S 3 (0, 8) S 2 (0, 4) If added Right-to-left connections could support Rotate (not in MIPS but found in ISAs)

Barrel Shifter Technology-dependent solutions: 1 transistor per switch: D3 D2 D1 D0 A2 A1 A0 A3 SR0 SR1 SR2 SR3 Qi are data input Di are output SRi are control lines that make connection Can do N x N shifter in N**2 transistors: 32x32 = 1024 transistors Simplicity lead to inclusion even if large shifts are rare

What about adders? Impractical to represent by truth table 32 A + C B A[0] A[1] .... A[31] B[0] ....... B[31] C[0] C[1] .... C[31] Impractical to represent by truth table Exponential in number of input bits

Adders are special ..... We’ll talk about them later Also, multipliers Let’s just assume they exist

Subtract ? A - B ? = A + NOT (B) + 1 Yes, there’s an easier way... A + 32 A + 32 1 B 32 + 1

Controllable Add / Sub ? A B Add Subtract Choose

How it’s really done 32 A + 32 B =1 Carry in Choose

What’s the point of this ? 32 ALU Control points The ALU is combinational Must have control signals to choose!

32-bit wide inverter ? 1 1 1 1 1 Easier to draw! In bit[31] Out bit[31] In bit[30] 1 Out bit[30] In bit[1] 1 Out bit[1] In bit[0] 1 Out bit[0] 32 32 1 Easier to draw!

Same idea : 32 - bit wide multiplexors 32 - bit wide clocked registers, such as the Program counter write back data register 32 D Q 32 Clock signal not drawn

Memories ? We’ll treat these as combinational Register file Instruction memory Data memory We’ll treat these as combinational (not “clocked”)