Electrical Engineering Dept. Catholic University - PUCRS, Porto Alegre, Brazil Space Science Centre School of Engineering University of Sussex, England Merging BIST and Configurable Computing Technology to Improve Availability in Space Applications Eduardo Bezerra 1, Fabian Vargas 2, Michael Paul Gough 3 1, 3 Space Science Centre, University of Sussex, Brighton, BN1 9QT, England E.A.Bezerra@sussex.ac.uk, M.P.Gough@sussex.ac.uk 1, 2 Catholic University - PUCRS, 90619-900 Porto Alegre - Brazil vargas@computer.org 1st IEEE Latin American test Workshop - LATW’00. Marina Palace Hotel, March 13-15, 2000. Rio de Janeiro, Brazil

Agenda 1 - Preliminaries 2 - Case study FPGA 1 - Preliminaries 2 - Case study 3 - Improving the case study reliability 4 - Improving the case study testability 5 - Expected results 6 - Conclusions

Spatial vs. Temporal computation Microprocessor - Software 1 - Preliminaries Spatial vs. Temporal computation main() { int a, b, c, d, x; a = 3; b = 2; c = 1; d = 3; x = (a | b) & (c | d); } FPGA - Hardware Spatial computation Microprocessor - Software Temporal computation mov A, 3 or A, 2 mov D, A mov A, 1 or A, 3 and A, D mov x, A X C D B A

Configurable computing Reconfigurable computing 1 - Preliminaries Configurable computing HW can be modified according to the application Satellite module: device X, with configuration 1 ABS controller: device X, with configuration 2 Application n: device X, with configuration n … Reconfigurable computing HW can be modified, on-line, according to the application requirements Data processing for instrument 1: configuration 1 Data processing for instrument 2: configuration 2 House Keeping: configuration 3 Space data communications: configuration 4 … t (ms) 480 560 600 693 More information: http://www.sciam.com/0697issue/0697villasenor.html

1 - Preliminaries Field Programmable Gate Array (FPGA): The best option available to implement a configurable computer system. I/O Block Din X a b F c LUT Y d G e Configurable Logic Block Programmable Interconnections

VHDL/FPGA version of an on-board computer module. 2 - Case study VHDL/FPGA version of an on-board computer module. Designed/implemented at Sussex. Flew on a Nasa’s sounding rocket. Telemetry request (HF) . I/P1 FIFO2 512x9 FSM2 Microcontroller (HF) Parallel to serial Telemetry output (HF) . I/P2 FSM1 FIFO1 512x9 . Next energy step FIFO2 512x9 Parallel to serial . Last energy bits Microcontroller (LF) Parallel to serial FIFO1 512x9 Telemetry output (LF) Telemetry request (LF) Serial ROM (1 M Bits) 2 x XQ1701L Serial ROM (1 M Bits) XQ1701L Data CLK DIN PROG CLK FPGA XQ4085XL Telemetry Telecommands Application inputs

The auto-correlation function (ACF) implemented: 2 - Case study Main features: scientific application memory transfer high input sampling rate scarceness of processing modules typical microcontroller based embedded system The auto-correlation function (ACF) implemented:

1st action: use of high-reliable military devices 3 - Improving the case study reliability 1st action: use of high-reliable military devices The XQ4000XL Family XQ4013XL (10K to 30K usable gates) XQ4036XL (20K to 65K usable gates) XQ4062XL (40K to 130K usable gates) XQ4085XL (55K to 180K usable gates) The XQV Virtex Family XQV100 (30K to 100K usable gates) XQV300 (80K to 300K usable gates) XQV600 (185K to 600K usable gates) XQV1000 (330K to 1M usable gates) Temperature range -55 ºC to +125 ºC http://www.xilinx.com/products/hirel_qml.htm

2nd action: use of FT strategies 3 - Improving the case study reliability 2nd action: use of FT strategies Sources of logic faults in FPGA systems cosmic radiation manufacturing/operating imperfections Adoption of a fault model stuck-at connectivity IONIZATION COLUMM . FAST CHARGED PARTICLE DEFLECTION REGION Radiation causes Single Event Upsets Latches are Sensitive to SEUs Xilinx FPGAs store logic/routing in latches

1 - TMR with a voter using the FPGA readback capability 3 - Improving the case study reliability SEU tolerance 1 - TMR with a voter using the FPGA readback capability Configuration bitstream Vote FPGA FPGA Readback bitstream: user registers user logic routing

2 - “Refresh” without TMR 3 - Improving the case study reliability SEU tolerance 2 - “Refresh” without TMR Serial ROM counter <= counter + 1; if counter = 0 then PROG <= ‘0’; -- reset else PROG <= ‘1’; end if; Configuration bitstream Application process counter Application process Application process FPGA

Strategies for connectivity faults 3 - Improving the case study reliability Strategies for connectivity faults library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity VOTER is port (CLK_IN : in std_logic; RESET_NEG_IN : in std_logic; IP1_IN : in std_logic; IP2_IN : in std_logic; IP3_IN : in std_logic; OUT_OUT : out std_logic; ERROR_OUT : out std_logic ); end VOTER; architecture VOTER_BEH of VOTER is begin ERROR_OUT <= '0' when RESET_NEG_IN = '0' else '1' when ((IP1_IN /= IP2_IN) or (IP1_IN /= IP3_IN) or (IP2_IN /= IP3_IN)) else '0'; VOTER_PRO: process (CLK_IN, RESET_NEG_IN) if RESET_NEG_IN = '0' then OUT_OUT <= '0'; elsif CLK_IN'event and CLK_IN = '1' then if (IP1_IN = IP2_IN) or (IP1_IN = IP3_IN) then OUT_OUT <= IP1_IN; elsif IP2_IN = IP3_IN then OUT_OUT <= IP2_IN; end if; end process VOTER_PRO; end VOTER_BEH; Application process Application process Application process K e r n l FPGA

Improving reliability with external hardware 3 - Improving the case study reliability Improving reliability with external hardware Serial ROM (2 M Bits) 2 x XQ1701L Data CLK Serial ROM (2 M Bits) 2 x XQ1701L Data CLK Serial ROM (2 M Bits) 2 x XQ1701L Data CLK RAM (8 M Bits) Control Address Data CPLD Control signals CCLK PROG DIN FPGA XQ4085XL Telemetry Telecommands Application inputs Case 1: Serial ROMs with the same configuration bitstream Case 2: Serial ROMs with different configuration bitstream

X = (A + B) * (C + D) Reserved area 3 - Improving the case study reliability X = (A + B) * (C + D) A B X C A D B X C D A B C X D Reserved area

The Reliability Evaluation of the System for Case 1 and Case 2 3 - Improving the case study reliability The Reliability Evaluation of the System for Case 1 and Case 2

4 - Improving the case study testability Test options: Fault detection on ground - problem: time spent transmitting data Fault detection on board - problem: definition of a minimum test set Mutation analysis technique: VHDL program is a chromosome syntactic changes in the program  malign genes in mutated chromosomes generate a large number of mutated programs for the original program generate a large set of test vectors for the original VHDL program test vectors are mutation-adequated for a program, if they can distinguish the program from programs that differ from it by small syntactic changes

5 - Expected results Expected performance

Area usage remarks 5 - Expected results RAM implementation is the most consuming area module VHDL/FPGA allows to use only the amount of memory needed Multiplication: a 16x16 pre-optimised multiplier occupies 213 CLBs the ‘*’ operator in VHDL consumes 215 CLBs use of the ‘*’ operator to have all the system described in VHDL

6 - Conclusions Synthesis tools available for high level languages (e.g. VHDL behavioural and Verilog) are still not efficient VHDL developer has to follow strict rules Adequate description language to be used Development of a library with special components Development of an FPGA board to test the FT strategies HDL deserves deeper investigation