B.Sc. Thesis by Çağrı Gürleyük Noise Analysis and Simulation of a Two-Step Successive Approximation ADC B.Sc. Thesis by Çağrı Gürleyük 040060345 27.05.2018

Introduction Two-step Successive Approximation Register Analog to Digital Converter Noise Analysis Noise Analysis of a Switched Track and Hold Noise Analysis of a Switched Amplifier Noise Analysis of the SAR ADC 27.05.2018

Motivation of the Thesis Develop a method of analysis for a simple circuit (switched capacitor track and hold) and correleate it with simulation results. Develop a method of analysis for a more complex circuit (switched capacitor amplifier) and correleate it with simulation results. Having correleated analysis and simulation; apply the method to a more complex, hard to analyze circuit. 27.05.2018

The Successive Approximation ADC Nyquist-rate data converter implementing the binary search algorithm. Suitable for medium-resolution, medium-speed applications. Uses digital logic to implement the SAR algorithm. Uses an analog sample and hold, comparator, and DAC. 27.05.2018

Noise Analysis Continuous Time Linear Time Invarient Circuits Inherently linear (if the opamp is assumed to be so.) SPICE NOISE analysis runs on linear circuits; thus a perfect match. 27.05.2018

Noise Analysis Resistor noise filtered by a capacitor. Integration of noise yields vn2 = kT/C. 27.05.2018

Noise Analysis What about a switched circuit? Has two (or more) steady state operating points, which due to charge transfer between capacitors, have transient effects. 27.05.2018

Simulating Noise in Switched Capacitor Circuits PSS and PNOISE from SpectreRF Transient Noise from Spectre Introduces the concept of a periodic operating point. (Periodic Steady State) Uses frequency domain decomposition to assess the behaviour of the circuit at its ‘periodic’ operating point and its harmonics. Higher frequency components mean increased simulation time. Uses traditional transient analysis methods, by injecting noise. Solves nonlinear device equations, most accurate device representations Higher noise frequency means reduced simulation steps, thus increased simulation time. 27.05.2018

Analyzing the Switched Capacitor Track and Hold The simplest imaginable switched circuit with a periodic operating point. 27.05.2018

Analyzing the Switched Capacitor Track and Hold Sampling operation results in aliasing. Integrated noise figure: vn2 = kT/C 27.05.2018

PNOISE Simulation Small-signal analysis over a periodic operating point. Sinc colored noise spectrum. Integrating yields kT/C. 27.05.2018

Transient Noise Simulation Frequency spectrum is obtained by coherent sampling. Power is extracted by IQ Modulation. Integrated to yield kT/C. 27.05.2018

Which one to choose? Transient Noise. Both noise simulation methodologies were compared; along with the time required to run a simulation to achieve reasonable results. The integration requires a very high frequency simulation; and PNOISE maximum sidebands parameter increases drastically; resulting in very long simulation times. For simulations with a larger number of elements (i.e. A complete chip) PNOISE simulation may still be viable, simulation-time wise. 27.05.2018

Analyzing the Switched Capacitor Amplifier Extends the analysis of the switched capacitor track and hold. 27.05.2018

Analyzing the Switched Capacitor Amplifier Noise sources are identified in each phase, referred to the output and integrated. Sampling Phase Evaluation Phase The noise process. In the sampling phase, the noise is stored on the capacitors by the sampling switches; in the evaluation phase, this noise is referred to the output with the power gain of the respective element. Also, the effects of the opamp noise; and the noise of the evaluation phase switches are included. In the evaluation phase, the bandwidth is determined by the GBW of the amplifier; so, the resistive effects of the noisy switches are ignored. 27.05.2018

Analyzing the Switched Capacitor Amplifier - Continued An analytical expression is reached for the noise behavior of the switched capacitor amplifier. Further simplification (identifying the dominatnt noise sources) lets us arrive at a clear noise optimization strategy. 27.05.2018

Simulating the Switched Capacitor Amplifier Simulation methods derived earlier are utilized to match analytical equations with simulation results. 27.05.2018

A Milestone in the Thesis At this point; having correlated simulation results with our analysis; we had developed a methodology of simulation for noise in switched capacitor circuits. We then moved on to the actual circuit that we wanted to analyze; the 14-bit, two-step, successive approximation ADC. 27.05.2018

Noise Model for the Two-Step SAR ADC - Flowchart The noise of SAR1 is compensated in the stage SAR2 due to the nature of the two step structure. SAR2 does present noise (comparator noise) but a properly designed comparator will have much less noise than the noise introduced by the other stages. 27.05.2018

Noise Model for the Two-Step SAR ADC Three phases are modeled; sampling, amplification and resampling. This is a simplified noise model for the SAR ADC. Four clock phases exist to achieve the Sampling, Amplification and Resampling phases. 27.05.2018

Substituting in the CMOS Operational Amplifier Fully-Differential OPAMP with NMOS input, class AB output stage, continuous time CMFB. Parameter Value Open Loop Gain 125 dB GBW 56MHz Phase Margin 56 deg. Power Consumption 3.13 mW 27.05.2018

Substituting in the CMOS Operational Amplifier – Adaptive Compensastion The capacitve load of the amplifier changes in the amplification and resampling stages. In the amplification stage, the opamp is used to provide a gain of 64; which also reduces compensation requirement. To achieve stability in the resampling state, and speed in the amplification state; adaptive compensation. 27.05.2018

Simulating the Switched Capacitor Amplifier with the CMOS OPAMP Noise floor increases with the added noise of the CMOS OPAMP. Integrated noise is found to be 10.68uV2, resulting in a 3.3mV effective noise voltage; lower than one LSB of the converter. 27.05.2018

Simulation Results for the Two-Step SAR ADC Integrated noise is found to be 17.11uV2, resulting in a 4.1mV effective noise voltage; lower than one LSB of the converter. 27.05.2018